diff --git a/dts/bindings/spi/spi-device.yaml b/dts/bindings/spi/spi-device.yaml
index 8598f73b388..e529ba5c146 100644
--- a/dts/bindings/spi/spi-device.yaml
+++ b/dts/bindings/spi/spi-device.yaml
@@ -16,3 +16,16 @@ properties:
       description: Maximum clock frequency of device's SPI interface in Hz
     label:
       required: true
+    duplex:
+      type: int
+      required: false
+      description: |
+        Duplex mode, full or half. By default it's always full duplex thus 0
+        as this is, by far, the most common mode.
+        Use the macros not the actual enum value, here is the concordance
+        list (see dt-bindings/spi/spi.h)
+          0    SPI_FULL_DUPLEX
+          2048 SPI_HALF_DUPLEX
+      enum:
+        - 0
+        - 2048
diff --git a/include/drivers/spi.h b/include/drivers/spi.h
index f110e62d6b3..96aef7f60d5 100644
--- a/include/drivers/spi.h
+++ b/include/drivers/spi.h
@@ -22,6 +22,7 @@
 #include <zephyr/types.h>
 #include <stddef.h>
 #include <device.h>
+#include <dt-bindings/spi/spi.h>
 #include <drivers/gpio.h>
 
 #ifdef __cplusplus
@@ -84,15 +85,6 @@ extern "C" {
 #define SPI_WORD_SET(_word_size_)		\
 	((_word_size_) << SPI_WORD_SIZE_SHIFT)
 
-/**
- * @brief SPI duplex modes
- *
- * Some controllers support half duplex transfer, which results in 3-wire usage.
- * By default, full duplex will prevail.
- */
-#define SPI_FULL_DUPLEX		(0U << 11)
-#define SPI_HALF_DUPLEX		(1U << 11)
-
 /**
  * @brief Specific SPI devices control bits
  */
diff --git a/include/dt-bindings/spi/spi.h b/include/dt-bindings/spi/spi.h
new file mode 100644
index 00000000000..f9be18c6d51
--- /dev/null
+++ b/include/dt-bindings/spi/spi.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
+
+/**
+ * @brief SPI Interface
+ * @defgroup spi_interface SPI Interface
+ * @ingroup io_interfaces
+ * @{
+ */
+
+/**
+ * @brief SPI duplex mode
+ *
+ * Some controllers support half duplex transfer, which results in 3-wire usage.
+ * By default, full duplex will prevail.
+ */
+#define SPI_FULL_DUPLEX		(0U << 11)
+#define SPI_HALF_DUPLEX		(1U << 11)
+
+/**
+ * @}
+ */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_ */