diff --git a/boards/arc/emsdp/doc/index.rst b/boards/arc/emsdp/doc/index.rst index 4747cbd1944..b02c2539ef5 100644 --- a/boards/arc/emsdp/doc/index.rst +++ b/boards/arc/emsdp/doc/index.rst @@ -98,6 +98,30 @@ Note: DW SPI only available on SPI0 and SPI1. whole flash then write 4 byte data to the flash. Read from the flash and compare the result with buffer to check functionality. +Pinmux interface +================ + +The following pinmux peripheral module standards are supported: + +* Digilent Pmod (3x) + +The ARC EM SDP features three 12-pin Pmod connectors: Pmod_A, Pmod_B, and Pmod_C. +The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, +I2C, and PWM (Note: support two type UART Pmod interface: UARTA is newer version). +Multiplexing is controlled by software using the PMOD_MUX_CTRL register. + +* Arduino (1x) + +The ARC EM SDP provides an Arduino shield interface. Multiplexing is controlled by software +using the ARDUINO_MUX_CTRL register. Note: some IO must be programmed in group and can't be +set individually, for details see Table 9 in `EM Software Development Platform user guide`_. + +* MikroBUS (1x) + +Note that since the controllers that are mapped to the MikroBUS are shared with the Arduino +controllers, and therefore the MikroBUS functions are only available when the Arduino +multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO). + Programming and Debugging ************************* @@ -252,6 +276,9 @@ References .. target-notes:: +.. _EM Software Development Platform user guide: + https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform + .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules diff --git a/boards/arc/emsdp/emsdp-pinctrl.dtsi b/boards/arc/emsdp/emsdp-pinctrl.dtsi new file mode 100644 index 00000000000..efe492a4b2a --- /dev/null +++ b/boards/arc/emsdp/emsdp-pinctrl.dtsi @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include + +&pinctrl { + /* PMOD_A */ + pmodA_gpio: pmodA_gpio { + pinmux = ; + }; + pmodA_uarta: pmodA_uarta { + pinmux = ; + }; + pmodA_uartb: pmodA_uartb { + pinmux = ; + }; + pmodA_spi1_cs0: pmodA_spi1_cs0 { + pinmux = ; + }; + pmodA_i2c2: pmodA_i2c2 { + pinmux = ; + }; + pmodA_pwm1: pmodA_pwm1 { + pinmux = ; + }; + pmodA_pwm2: pmodA_pwm2 { + pinmux = ; + }; + + /* PMOD_B */ + pmodB_gpio: pmodB_gpio { + pinmux = ; + }; + pmodB_uarta: pmodB_uarta { + pinmux = ; + }; + pmodB_uartb: pmodB_uartb { + pinmux = ; + }; + pmodB_spi1_cs1: pmodB_spi1_cs1 { + pinmux = ; + }; + pmodB_i2c2: pmodB_i2c2 { + pinmux = ; + }; + pmodB_pwm1: pmodB_pwm1 { + pinmux = ; + }; + pmodB_pwm2: pmodB_pwm2 { + pinmux = ; + }; + + /* PMOD_C */ + pmodC_gpio: pmodC_gpio { + pinmux = ; + }; + pmodC_uarta: pmodC_uarta { + pinmux = ; + }; + pmodC_uartb: pmodC_uartb { + pinmux = ; + }; + pmodC_spi1_cs2: pmodC_spi1_cs2 { + pinmux = ; + }; + pmodC_i2c2: pmodC_i2c2 { + pinmux = ; + }; + pmodC_pwm1: pmodC_pwm1 { + pinmux = ; + }; + pmodC_pwm2: pmodC_pwm2 { + pinmux = ; + }; + + /* ARDUINO_PIN_1 */ + arduino_CFG0_gpio: arduino_CFG0_gpio { + pinmux = ; + }; + arduino_CFG0_uart: arduino_CFG0_uart { + pinmux = ; + }; + + /* ARDUINO_PIN_3 */ + arduino_CFG1_gpio: arduino_CFG1_gpio { + pinmux = ; + }; + arduino_CFG1_pwm: arduino_CFG1_pwm{ + pinmux = ; + }; + + /* ARDUINO_PIN_5 */ + arduino_CFG2_gpio: arduino_CFG2_gpio { + pinmux = ; + }; + arduino_CFG2_pwm: arduino_CFG2_pwm { + pinmux = ; + }; + + /* ARDUINO_PIN_7 */ + arduino_CFG3_gpio: arduino_CFG3_gpio { + pinmux = ; + }; + arduino_CFG3_pwm: arduino_CFG3_pwm { + pinmux = ; + }; + + /* ARDUINO_PIN_9 */ + arduino_CFG4_gpio: arduino_CFG4_gpio { + pinmux = ; + }; + arduino_CFG4_pwm: arduino_CFG4_pwm { + pinmux = ; + }; + + /* ARDUINO_PIN_13 */ + arduino_CFG5_gpio: arduino_CFG5_gpio { + pinmux = ; + }; + arduino_CFG5_spi: arduino_CFG5_spi { + pinmux = ; + }; + arduino_CFG5_pwm: arduino_CFG5_pwm { + pinmux = ; + }; + + /* ARDUINO_PIN_AD5 */ + arduino_CFG6_gpio: arduino_CFG6_gpio { + pinmux = ; + }; + arduino_CFG6_i2c: arduino_CFG6_i2c { + pinmux = ; + }; +}; diff --git a/boards/arc/emsdp/emsdp.dts b/boards/arc/emsdp/emsdp.dts index 4cb95a39857..8976ddc3422 100644 --- a/boards/arc/emsdp/emsdp.dts +++ b/boards/arc/emsdp/emsdp.dts @@ -9,6 +9,7 @@ #include #include #include "board.dtsi" +#include "emsdp-pinctrl.dtsi" / { model = "emsdp"; @@ -49,5 +50,17 @@ spi@f1000000 { interrupts = <84 1>; }; + + spi@80010000 { + interrupts = <63 2>, <64 2>, <65 2>; + pinctrl-0 = <&arduino_CFG5_spi>; + pinctrl-names = "default"; + }; + + spi@80010100 { + interrupts = <67 2>, <68 2>, <69 2>; + pinctrl-0 = <&pmodA_spi1_cs0>; + pinctrl-names = "default"; + }; }; }; diff --git a/boards/arc/emsdp/emsdp_defconfig b/boards/arc/emsdp/emsdp_defconfig index 031a0ebe6ad..2480ef52f3b 100644 --- a/boards/arc/emsdp/emsdp_defconfig +++ b/boards/arc/emsdp/emsdp_defconfig @@ -16,3 +16,4 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_ARC_MPU_ENABLE=y CONFIG_GPIO=y CONFIG_SPI=y +CONFIG_PINCTRL=y diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index f7a65a664c9..0f18755a24c 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -30,3 +30,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 19d72843efa..0c1f4c05b2f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -59,5 +59,6 @@ source "drivers/pinctrl/Kconfig.xmc4xxx" source "drivers/pinctrl/Kconfig.nxp_s32" source "drivers/pinctrl/Kconfig.gecko" source "drivers/pinctrl/Kconfig.ti_k3" +source "drivers/pinctrl/Kconfig.emsdp" endif # PINCTRL diff --git a/drivers/pinctrl/Kconfig.emsdp b/drivers/pinctrl/Kconfig.emsdp new file mode 100644 index 00000000000..825ec0f0230 --- /dev/null +++ b/drivers/pinctrl/Kconfig.emsdp @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Synopsys +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_EMSDP + bool "EMSDP pinmux driver" + default y + depends on DT_HAS_SNPS_EMSDP_PINCTRL_ENABLED + help + Enable driver for the synopsys ARC EMSDP pinctrl driver diff --git a/drivers/pinctrl/pinctrl_emsdp.c b/drivers/pinctrl/pinctrl_emsdp.c new file mode 100644 index 00000000000..d19f850b37f --- /dev/null +++ b/drivers/pinctrl/pinctrl_emsdp.c @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2023 Synopsys + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT snps_emsdp_pinctrl + +#include +#include +#include +#include + +#define EMSDP_CREG_BASE DT_INST_REG_ADDR(0) +#define EMSDP_CREG_PMOD_MUX_OFFSET (0x0030) + +#define MUX_SEL0_OFFSET (0) +#define MUX_SEL1_OFFSET (4) +#define MUX_SEL2_OFFSET (8) +#define MUX_SEL3_OFFSET (12) +#define MUX_SEL4_OFFSET (16) +#define MUX_SEL5_OFFSET (20) +#define MUX_SEL6_OFFSET (24) +#define MUX_SEL7_OFFSET (28) + +#define MUX_SEL0_MASK (0xf << MUX_SEL0_OFFSET) +#define MUX_SEL1_MASK (0xf << MUX_SEL1_OFFSET) +#define MUX_SEL2_MASK (0xf << MUX_SEL2_OFFSET) +#define MUX_SEL3_MASK (0xf << MUX_SEL3_OFFSET) +#define MUX_SEL4_MASK (0xf << MUX_SEL4_OFFSET) +#define MUX_SEL5_MASK (0xf << MUX_SEL5_OFFSET) +#define MUX_SEL6_MASK (0xf << MUX_SEL6_OFFSET) +#define MUX_SEL7_MASK (0xf << MUX_SEL7_OFFSET) + +/** + * PMOD A Multiplexor + */ +#define PM_A_CFG0_GPIO ((0) << MUX_SEL0_OFFSET) +#define PM_A_CFG0_I2C ((1) << MUX_SEL0_OFFSET) /* io_i2c_mst2 */ +#define PM_A_CFG0_SPI ((2) << MUX_SEL0_OFFSET) /* io_spi_mst1, cs_0 */ +#define PM_A_CFG0_UART1a ((3) << MUX_SEL0_OFFSET) /* io_uart1 */ +#define PM_A_CFG0_UART1b ((4) << MUX_SEL0_OFFSET) /* io_uart1 */ +#define PM_A_CFG0_PWM1 ((5) << MUX_SEL0_OFFSET) +#define PM_A_CFG0_PWM2 ((6) << MUX_SEL0_OFFSET) + +#define PM_A_CFG1_GPIO ((0) << MUX_SEL1_OFFSET) + +/** + * PMOD B Multiplexor + */ +#define PM_B_CFG0_GPIO ((0) << MUX_SEL2_OFFSET) +#define PM_B_CFG0_I2C ((1) << MUX_SEL2_OFFSET) /* io_i2c_mst2 */ +#define PM_B_CFG0_SPI ((2) << MUX_SEL2_OFFSET) /* io_spi_mst1, cs_1 */ +#define PM_B_CFG0_UART2a ((3) << MUX_SEL2_OFFSET) /* io_uart2 */ +#define PM_B_CFG0_UART2b ((4) << MUX_SEL2_OFFSET) /* io_uart2 */ +#define PM_B_CFG0_PWM1 ((5) << MUX_SEL2_OFFSET) +#define PM_B_CFG0_PWM2 ((6) << MUX_SEL2_OFFSET) + +#define PM_B_CFG1_GPIO ((0) << MUX_SEL3_OFFSET) + +/** + * PMOD C Multiplexor + */ +#define PM_C_CFG0_GPIO ((0) << MUX_SEL4_OFFSET) +#define PM_C_CFG0_I2C ((1) << MUX_SEL4_OFFSET) /* io_i2c_mst2 */ +#define PM_C_CFG0_SPI ((2) << MUX_SEL4_OFFSET) /* io_spi_mst1, cs_2 */ +#define PM_C_CFG0_UART3a ((3) << MUX_SEL4_OFFSET) /* io_uart3 */ +#define PM_C_CFG0_UART3b ((4) << MUX_SEL4_OFFSET) /* io_uart3 */ +#define PM_C_CFG0_PWM1 ((5) << MUX_SEL4_OFFSET) +#define PM_C_CFG0_PWM2 ((6) << MUX_SEL4_OFFSET) + +#define PM_C_CFG1_GPIO ((0) << MUX_SEL5_OFFSET) + +/** + * Arduino Multiplexor + */ +#define ARDUINO_CFG0_GPIO ((0) << MUX_SEL0_OFFSET) +#define ARDUINO_CFG0_UART ((1) << MUX_SEL0_OFFSET) /* io_uart0 */ + +#define ARDUINO_CFG1_GPIO ((0) << MUX_SEL1_OFFSET) +#define ARDUINO_CFG1_PWM ((1) << MUX_SEL1_OFFSET) + +#define ARDUINO_CFG2_GPIO ((0) << MUX_SEL2_OFFSET) +#define ARDUINO_CFG2_PWM ((1) << MUX_SEL2_OFFSET) + +#define ARDUINO_CFG3_GPIO ((0) << MUX_SEL3_OFFSET) +#define ARDUINO_CFG3_PWM ((1) << MUX_SEL3_OFFSET) + +#define ARDUINO_CFG4_GPIO ((0) << MUX_SEL4_OFFSET) +#define ARDUINO_CFG4_PWM ((1) << MUX_SEL4_OFFSET) + +#define ARDUINO_CFG5_GPIO ((0) << MUX_SEL5_OFFSET) +#define ARDUINO_CFG5_SPI ((1) << MUX_SEL5_OFFSET) /* io_spi_mst0, cs_0 */ +#define ARDUINO_CFG5_PWM1 ((2) << MUX_SEL5_OFFSET) +#define ARDUINO_CFG5_PWM2 ((3) << MUX_SEL5_OFFSET) +#define ARDUINO_CFG5_PWM3 ((4) << MUX_SEL5_OFFSET) + +#define ARDUINO_CFG6_GPIO ((0) << MUX_SEL6_OFFSET) +#define ARDUINO_CFG6_I2C ((1) << MUX_SEL6_OFFSET) /* io_i2c_mst1 */ + +static int pinctrl_emsdp_set(uint32_t pin, uint32_t type) +{ + const uint32_t mux_regs = (EMSDP_CREG_BASE + EMSDP_CREG_PMOD_MUX_OFFSET); + uint32_t reg; + + if (pin <= PMOD_C) { + reg = sys_read32(mux_regs + PMOD_MUX_CTRL); + } else { + reg = sys_read32(mux_regs + ARDUINO_MUX_CTRL); + } + + switch (pin) { + case PMOD_A: + reg &= ~(MUX_SEL0_MASK); + switch (type) { + case PMOD_GPIO: + reg |= PM_A_CFG0_GPIO; + break; + case PMOD_UARTA: + reg |= PM_A_CFG0_UART1a; + break; + case PMOD_UARTB: + reg |= PM_A_CFG0_UART1b; + break; + case PMOD_SPI: + reg |= PM_A_CFG0_SPI; + break; + case PMOD_I2C: + reg |= PM_A_CFG0_I2C; + break; + case PMOD_PWM_MODE1: + reg |= PM_A_CFG0_PWM1; + break; + case PMOD_PWM_MODE2: + reg |= PM_A_CFG0_PWM2; + break; + default: + break; + } + break; + case PMOD_B: + reg &= ~(MUX_SEL2_MASK); + switch (type) { + case PMOD_GPIO: + reg |= PM_B_CFG0_GPIO; + break; + case PMOD_UARTA: + reg |= PM_B_CFG0_UART2a; + break; + case PMOD_UARTB: + reg |= PM_A_CFG0_UART1b; + break; + case PMOD_SPI: + reg |= PM_B_CFG0_SPI; + break; + case PMOD_I2C: + reg |= PM_B_CFG0_I2C; + break; + case PMOD_PWM_MODE1: + reg |= PM_B_CFG0_PWM1; + break; + case PMOD_PWM_MODE2: + reg |= PM_B_CFG0_PWM2; + break; + default: + break; + } + break; + case PMOD_C: + reg &= ~(MUX_SEL4_MASK); + switch (type) { + case PMOD_GPIO: + reg |= PM_C_CFG0_GPIO; + break; + case PMOD_UARTA: + reg |= PM_C_CFG0_UART3a; + break; + case PMOD_UARTB: + reg |= PM_C_CFG0_UART3b; + break; + case PMOD_SPI: + reg |= PM_C_CFG0_SPI; + break; + case PMOD_I2C: + reg |= PM_C_CFG0_I2C; + break; + case PMOD_PWM_MODE1: + reg |= PM_C_CFG0_PWM1; + break; + case PMOD_PWM_MODE2: + reg |= PM_C_CFG0_PWM2; + break; + default: + break; + } + break; + case ARDUINO_PIN_0: + case ARDUINO_PIN_1: + reg &= ~MUX_SEL0_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG0_GPIO; + } else if (type == ARDUINO_UART) { + reg |= ARDUINO_CFG0_UART; + } + break; + case ARDUINO_PIN_2: + case ARDUINO_PIN_3: + reg &= ~MUX_SEL1_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG1_GPIO; + } else if (type == ARDUINO_PWM) { + reg |= ARDUINO_CFG1_PWM; + } + break; + case ARDUINO_PIN_4: + case ARDUINO_PIN_5: + reg &= ~MUX_SEL2_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG2_GPIO; + } else if (type == ARDUINO_PWM) { + reg |= ARDUINO_CFG2_PWM; + } + break; + case ARDUINO_PIN_6: + case ARDUINO_PIN_7: + reg &= ~MUX_SEL3_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG3_GPIO; + } else if (type == ARDUINO_PWM) { + reg |= ARDUINO_CFG3_PWM; + } + break; + case ARDUINO_PIN_8: + case ARDUINO_PIN_9: + reg &= ~MUX_SEL4_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG4_GPIO; + } else if (type == ARDUINO_PWM) { + reg |= ARDUINO_CFG4_PWM; + } + break; + case ARDUINO_PIN_10: + case ARDUINO_PIN_11: + case ARDUINO_PIN_12: + case ARDUINO_PIN_13: + reg &= ~MUX_SEL5_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG5_GPIO; + } else if (type == ARDUINO_SPI) { + reg |= ARDUINO_CFG5_SPI; + } else if (type == ARDUINO_PWM) { + reg |= ARDUINO_CFG5_PWM1; + } + break; + case ARDUINO_PIN_AD4: + case ARDUINO_PIN_AD5: + reg &= ~MUX_SEL6_MASK; + if (type == ARDUINO_GPIO) { + reg |= ARDUINO_CFG6_GPIO; + } else if (type == ARDUINO_I2C) { + reg |= ARDUINO_CFG6_I2C; + } + break; + default: + break; + } + + if (pin <= PMOD_C) { + sys_write32(reg, mux_regs + PMOD_MUX_CTRL); + } else { + sys_write32(reg, mux_regs + ARDUINO_MUX_CTRL); + } + + return 0; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + int i; + + for (i = 0; i < pin_cnt; i++) { + pinctrl_emsdp_set(pins[i].pin, pins[i].type); + } + + return 0; +} diff --git a/dts/arc/synopsys/emsdp.dtsi b/dts/arc/synopsys/emsdp.dtsi index e5e0439c20f..375eb745594 100644 --- a/dts/arc/synopsys/emsdp.dtsi +++ b/dts/arc/synopsys/emsdp.dtsi @@ -101,6 +101,11 @@ status = "disabled"; }; + pinctrl: pinctrl@f0001000 { + compatible = "snps,emsdp-pinctrl"; + reg = <0xf0001000 0x100>; + }; + /* SPI-flash for user data */ spi1: spi@f1000000 { compatible = "snps,designware-spi"; @@ -120,5 +125,32 @@ }; }; + /* DFSS-SPI0 */ + spi2: spi@80010000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010000 0x100>; + clocks = <&spiclk>; + interrupts = <63 2>, <64 2>, <65 2>; + interrupt-names = "err_int", "rx_avail", "tx_req"; + interrupt-parent = <&intc>; + aux_reg; + fifo-depth = <16>; + }; + + /* DFSS-SPI1 */ + spi3: spi@80010100 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010100 0x100>; + clocks = <&spiclk>; + interrupts = <67 2>, <68 2>, <69 2>; + interrupt-names = "err_int", "rx_avail", "tx_req"; + interrupt-parent = <&intc>; + aux_reg; + fifo-depth = <16>; + }; }; }; diff --git a/dts/bindings/pinctrl/snps,emsdp-pinctrl.yaml b/dts/bindings/pinctrl/snps,emsdp-pinctrl.yaml new file mode 100644 index 00000000000..fb04e5d12c9 --- /dev/null +++ b/dts/bindings/pinctrl/snps,emsdp-pinctrl.yaml @@ -0,0 +1,39 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: | + Synopsys ARC EMSDP board Pin controller for Pmod and Arduino shield interface. + + Device pin configuration should be placed in the child nodes of this node. + Populate the 'pinmux' field with a pair consisting of a pin number and its IO + function. + + For example, setting PmodA to SPI would look like this: + + #include + + &pinctrl { + pmodA_spi1_cs0: pmodA_spi1_cs0 { + pinmux = ; + }; + }; + +compatible: "snps,emsdp-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the EMSDP pins + configuration. + + properties: + pinmux: + required: true + type: array + description: | + EMSDP pin's configuration (pin, IO function). diff --git a/include/zephyr/dt-bindings/pinctrl/emsdp-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/emsdp-pinctrl.h new file mode 100644 index 00000000000..1f6922f84e4 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/emsdp-pinctrl.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Synopsys + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EMSDP_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EMSDP_PINCTRL_H_ + +/** + * Mux Control Register Index + */ +#define PMOD_MUX_CTRL 0 /*!< 32-bits, offset 0x0 */ + +#define ARDUINO_MUX_CTRL 4 /*!< 32-bits, offset 0x4 */ + +#define PMOD_A 0 +#define PMOD_B 1 +#define PMOD_C 2 +#define ARDUINO_PIN_0 3 +#define ARDUINO_PIN_1 4 +#define ARDUINO_PIN_2 5 +#define ARDUINO_PIN_3 6 +#define ARDUINO_PIN_4 7 +#define ARDUINO_PIN_5 8 +#define ARDUINO_PIN_6 9 +#define ARDUINO_PIN_7 10 +#define ARDUINO_PIN_8 11 +#define ARDUINO_PIN_9 12 +#define ARDUINO_PIN_10 13 +#define ARDUINO_PIN_11 14 +#define ARDUINO_PIN_12 15 +#define ARDUINO_PIN_13 16 +#define ARDUINO_PIN_AD0 17 +#define ARDUINO_PIN_AD1 18 +#define ARDUINO_PIN_AD2 19 +#define ARDUINO_PIN_AD3 20 +#define ARDUINO_PIN_AD4 21 +#define ARDUINO_PIN_AD5 22 + +#define PMOD_GPIO 0 +#define PMOD_UARTA 1 +#define PMOD_UARTB 2 +#define PMOD_SPI 3 +#define PMOD_I2C 4 +#define PMOD_PWM_MODE1 5 +#define PMOD_PWM_MODE2 6 +#define PMOD_PWM_MODE3 7 +#define ARDUINO_GPIO 8 +#define ARDUINO_UART 9 +#define ARDUINO_SPI 10 +#define ARDUINO_I2C 11 +#define ARDUINO_PWM 12 +#define ARDUINO_ADC 13 + + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EMSDP_PINCTRL_H_ */ diff --git a/soc/arc/snps_emsdp/pinctrl_soc.h b/soc/arc/snps_emsdp/pinctrl_soc.h new file mode 100644 index 00000000000..c0f7dc9809b --- /dev/null +++ b/soc/arc/snps_emsdp/pinctrl_soc.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Synopsys + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_ +#define ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_ + +#include +#include + +typedef struct pinctrl_soc_pin_t { + uint8_t pin; + uint8_t type; +} pinctrl_soc_pin_t; + +#define EMSDP_DT_PIN(node_id) \ + { \ + .pin = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .type = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + EMSDP_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#endif /* ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_ */