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drivers/interrupt_controller: Normalize DT aliases consitently for DW

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DT_<domain>_DW_<num>_<option> as for SPI, GPIO, DMA etc...

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2019-12-17 15:30:09 +01:00 • committed by Anas Nashif
commit 4b94668f5b
3 changed files with 18 additions and 14 deletions
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14
drivers/interrupt_controller/intc_dw.c
View file

@ -56,11 +56,11 @@ static void dw_ictl_isr(void *arg)
(struct dw_ictl_registers *)dw->base_addr;
dw_ictl_dispatch_child_isrs(regs->irq_maskstatus_l,
config->isr_table_offset);
config->isr_table_offset);
if (config->numirqs > 32) {
dw_ictl_dispatch_child_isrs(regs->irq_maskstatus_h,
config->isr_table_offset + 32);
config->isr_table_offset + 32);
}
}
@ -138,14 +138,14 @@ static int dw_ictl_intr_get_line_state(struct device *dev, unsigned int irq)
static void dw_ictl_config_irq(struct device *port);
static const struct dw_ictl_config dw_config = {
.irq_num = DT_DW_ICTL_IRQ,
.irq_num = DT_INTC_DW_0_BASE_ADDR,
.numirqs = DW_ICTL_NUM_IRQS,
.isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET,
.config_func = dw_ictl_config_irq,
};
static struct dw_ictl_runtime dw_runtime = {
.base_addr = DT_DW_ICTL_BASE_ADDR,
.base_addr = DT_ICTL_DW_0_BASE_ADDR,
};
static const struct irq_next_level_api dw_ictl_apis = {
@ -155,12 +155,12 @@ static const struct irq_next_level_api dw_ictl_apis = {
.intr_get_line_state = dw_ictl_intr_get_line_state,
};
DEVICE_AND_API_INIT(dw_ictl, CONFIG_DW_ICTL_NAME, dw_ictl_initialize,
DEVICE_AND_API_INIT(dw_ictl, DT_INTC_DW_0_NAME, dw_ictl_initialize,
&dw_runtime, &dw_config,
POST_KERNEL, CONFIG_DW_ICTL_INIT_PRIORITY, &dw_ictl_apis);
static void dw_ictl_config_irq(struct device *port)
{
IRQ_CONNECT(DT_DW_ICTL_IRQ, DT_DW_ICTL_IRQ_PRI, dw_ictl_isr,
DEVICE_GET(dw_ictl), DT_DW_ICTL_IRQ_FLAGS);
IRQ_CONNECT(DT_INTC_DW_0_IRQ, DT_INTC_DW_0_IRQ_PRI, dw_ictl_isr,
DEVICE_GET(dw_ictl), DT_INTC_DW_0_IRQ_FLAGS);
}

12
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -35,10 +35,14 @@
#define DT_CAVS_ICTL_3_IRQ_PRI DT_INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE
#define DT_DW_ICTL_BASE_ADDR DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DT_DW_ICTL_IRQ DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
#define DT_DW_ICTL_IRQ_PRI DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define DT_INTC_DW_0_BASE_ADDR \
DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DT_INTC_DW_0_NAME DT_SNPS_DESIGNWARE_INTC_81800_LABEL
#define DT_INTC_DW_0_IRQ DDT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
#define DT_INTC_DW_0_IRQ_PRI \
DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DT_INTC_DW_0_IRQ_FLAGS \
DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define DT_SPI_DW_0_BASE_ADDRESS \
DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS

6
soc/xtensa/intel_s1000/soc.c
View file

@ -54,7 +54,7 @@ void z_soc_irq_enable(u32_t irq)
switch (CAVS_IRQ_NUMBER(irq)) {
case DW_ICTL_IRQ_CAVS_OFFSET:
dev_ictl = device_get_binding(CONFIG_DW_ICTL_NAME);
dev_ictl = device_get_binding(DT_INTC_DW_0_NAME);
break;
default:
/* The source of the interrupt is in CAVS interrupt logic */
@ -112,7 +112,7 @@ void z_soc_irq_disable(u32_t irq)
switch (CAVS_IRQ_NUMBER(irq)) {
case DW_ICTL_IRQ_CAVS_OFFSET:
dev_ictl = device_get_binding(CONFIG_DW_ICTL_NAME);
dev_ictl = device_get_binding(DT_INTC_DW_0_NAME);
break;
default:
/* The source of the interrupt is in CAVS interrupt logic */
@ -179,7 +179,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
switch (CAVS_IRQ_NUMBER(irq)) {
case DW_ICTL_IRQ_CAVS_OFFSET:
dev_ictl = device_get_binding(CONFIG_DW_ICTL_NAME);
dev_ictl = device_get_binding(DT_INTC_DW_0_NAME);
break;
default:
/* The source of the interrupt is in CAVS interrupt logic */