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riscv32: riscv-privilege: Platform-Level Interrupt Controller support

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Updated the riscv-privilege SOC family to account for SOCs supporting
a Platform-level Interrupt Controller (PLIC) as specified by the
riscv privilege architecture.

riscv-privilege SOCs supporting a PLIC have to implement the following
list of APIs:
void riscv_plic_irq_enable(uint32_t irq);
void riscv_plic_irq_disable(uint32_t irq);
int riscv_plic_irq_is_enabled(uint32_t irq);
void riscv_plic_set_priority(uint32_t irq, uint32_t priority);
int riscv_plic_get_irq(void);

Change-Id: I0228574967348d572afc98a79257c697efc4309e
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This commit is contained in:
Jean-Paul Etienne 2017-03-14 22:13:58 +01:00 • committed by Andrew Boie
commit 4b8ae8863c
5 changed files with 51 additions and 1 deletions
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9
include/arch/riscv32/arch.h
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@ -72,11 +72,20 @@ void _irq_spurious(void *unused);
*
* @return The vector assigned to this interrupt
*/
#if defined(CONFIG_RISCV_HAS_PLIC)
#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
riscv_plic_set_priority(irq_p, priority_p); \
irq_p; \
})
#else
#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
irq_p; \
})
#endif
/*
* use atomic instruction csrrc to lock global irq