ITE drivers/interrupt_controller: add wuc interface
Add wakeup controller interface for ITE it8xxx2 chip. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
This commit is contained in:
Ruibin Chang
Marti Bolivar
parent
d66c1d9b54
commit
4b75cf8f47
11 changed files with 857 additions and 0 deletions
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@ -14,6 +14,7 @@ zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS intc_gicv3_its.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c)
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zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c)
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zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC intc_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC intc_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_WUC wuc_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_LEON_IRQMP intc_irqmp.c)
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zephyr_library_sources_ifdef(CONFIG_LEON_IRQMP intc_irqmp.c)
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zephyr_library_sources_ifdef(CONFIG_LOAPIC intc_loapic.c intc_system_apic.c)
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zephyr_library_sources_ifdef(CONFIG_LOAPIC intc_loapic.c intc_system_apic.c)
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zephyr_library_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR intc_loapic_spurious.S)
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zephyr_library_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR intc_loapic_spurious.S)
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@ -51,6 +51,10 @@ config INTC_INIT_PRIORITY
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help
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help
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Interrupt controller device initialization priority.
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Interrupt controller device initialization priority.
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module = INTC
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module-str = intc
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source "subsys/logging/Kconfig.template.log_config"
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source "drivers/interrupt_controller/Kconfig.multilevel"
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source "drivers/interrupt_controller/Kconfig.multilevel"
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source "drivers/interrupt_controller/Kconfig.loapic"
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source "drivers/interrupt_controller/Kconfig.loapic"
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@ -9,3 +9,15 @@ config ITE_IT8XXX2_INTC
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instance of the shared interrupt driver. To conserve RAM set
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instance of the shared interrupt driver. To conserve RAM set
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this value to the lowest practical value.
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this value to the lowest practical value.
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this software interrupt default set on by device tree.
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this software interrupt default set on by device tree.
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# Workaround for not being able to have commas in macro arguments
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DT_COMPAT_ITE_IT8XXX2_WUC := ite,it8xxx2-wuc
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config ITE_IT8XXX2_WUC
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bool "ITE it8xxx2 Wakeup controller (WUC) interface"
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depends on SOC_IT8XXX2
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default $(dt_compat_enabled,$(DT_COMPAT_ITE_IT8XXX2_WUC))
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help
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This option enables the wakeup controller interface for IT8XXX2
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family.
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This is required for KSCAN, UART, eSPI, GPIO etc., interrupt support.
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125
drivers/interrupt_controller/wuc_ite_it8xxx2.c
Normal file
125
drivers/interrupt_controller/wuc_ite_it8xxx2.c
Normal file
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@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2022 ITE Corporation. All Rights Reserved
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_wuc
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#include <device.h>
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#include <drivers/interrupt_controller/wuc_ite_it8xxx2.h>
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#include <dt-bindings/interrupt-controller/it8xxx2-wuc.h>
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#include <kernel.h>
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#include <soc.h>
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#include <soc_common.h>
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#include <stdlib.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(wuc_ite_it8xxx2, CONFIG_INTC_LOG_LEVEL);
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/* Driver config */
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struct it8xxx2_wuc_cfg {
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/* WUC wakeup edge mode register */
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uint8_t *reg_wuemr;
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/* WUC wakeup edge sense register */
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uint8_t *reg_wuesr;
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/* WUC wakeup enable register */
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uint8_t *reg_wuenr;
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/* WUC wakeup both edge mode register */
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uint8_t *reg_wubemr;
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};
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void it8xxx2_wuc_enable(const struct device *dev, uint8_t mask)
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{
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const struct it8xxx2_wuc_cfg *config = dev->config;
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volatile uint8_t *reg_wuenr = config->reg_wuenr;
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/*
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* WUC group only 1, 3, and 4 have enable/disable register,
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* others are always enabled.
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*/
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if (reg_wuenr == IT8XXX2_WUC_UNUSED_REG) {
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return;
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}
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/* Enable wakeup interrupt of the pin */
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*reg_wuenr |= mask;
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}
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void it8xxx2_wuc_disable(const struct device *dev, uint8_t mask)
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{
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const struct it8xxx2_wuc_cfg *config = dev->config;
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volatile uint8_t *reg_wuenr = config->reg_wuenr;
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/*
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* WUC group only 1, 3, and 4 have enable/disable register,
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* others are always enabled.
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*/
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if (reg_wuenr == IT8XXX2_WUC_UNUSED_REG) {
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return;
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}
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/* Disable wakeup interrupt of the pin */
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*reg_wuenr &= ~mask;
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}
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void it8xxx2_wuc_clear_status(const struct device *dev, uint8_t mask)
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{
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const struct it8xxx2_wuc_cfg *config = dev->config;
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volatile uint8_t *reg_wuesr = config->reg_wuesr;
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if (reg_wuesr == IT8XXX2_WUC_UNUSED_REG) {
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return;
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}
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/* W/C wakeup interrupt status of the pin */
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*reg_wuesr = mask;
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}
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void it8xxx2_wuc_set_polarity(const struct device *dev, uint8_t mask, uint32_t flags)
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{
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const struct it8xxx2_wuc_cfg *config = dev->config;
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volatile uint8_t *reg_wuemr = config->reg_wuemr;
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volatile uint8_t *reg_wubemr = config->reg_wubemr;
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if (reg_wuemr == IT8XXX2_WUC_UNUSED_REG) {
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return;
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}
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/* Set wakeup interrupt edge trigger mode of the pin */
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if ((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_RISING) {
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*reg_wubemr &= ~mask;
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*reg_wuemr &= ~mask;
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} else if ((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_FALLING) {
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*reg_wubemr &= ~mask;
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*reg_wuemr |= mask;
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} else {
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/* Both edge trigger mode */
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*reg_wubemr |= mask;
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}
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}
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static int it8xxx2_wuc_init(const struct device *dev)
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{
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return 0;
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}
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#define IT8XXX2_WUC_INIT(inst) \
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\
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static const struct it8xxx2_wuc_cfg it8xxx2_wuc_cfg_##inst = { \
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.reg_wuemr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_wuesr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.reg_wuenr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 2), \
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.reg_wubemr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 3), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&it8xxx2_wuc_init, \
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NULL, \
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NULL, \
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&it8xxx2_wuc_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(IT8XXX2_WUC_INIT)
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13
dts/bindings/interrupt-controller/ite,it8xxx2-wuc-map.yaml
Normal file
13
dts/bindings/interrupt-controller/ite,it8xxx2-wuc-map.yaml
Normal file
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@ -0,0 +1,13 @@
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# Copyright 2022 ITE Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: ITE Wake-Up Controller (WUC) mapping child node
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compatible: "ite,it8xxx2-wuc-map"
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child-binding:
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description: Child node to present the mapping between input of WUC and its source device
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properties:
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wucs:
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type: phandle-array
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required: true
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28
dts/bindings/interrupt-controller/ite,it8xxx2-wuc.yaml
Normal file
28
dts/bindings/interrupt-controller/ite,it8xxx2-wuc.yaml
Normal file
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@ -0,0 +1,28 @@
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# Copyright 2022 ITE Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: ITE Wake-Up Controller (WUC)
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compatible: "ite,it8xxx2-wuc"
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include: [base.yaml]
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properties:
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reg:
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required: true
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label:
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required: true
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"wakeup-controller":
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type: boolean
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required: true
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description: conveys that this node is a wakeup controller
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"#wuc-cells":
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type: int
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required: true
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description: number of items to expect in a wakeup controller specifier
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const: 1
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wuc-cells:
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- mask
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@ -8,6 +8,7 @@
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#include <mem.h>
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#include <mem.h>
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#include <dt-bindings/dt-util.h>
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#include <dt-bindings/dt-util.h>
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#include <dt-bindings/interrupt-controller/ite-intc.h>
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#include <dt-bindings/interrupt-controller/ite-intc.h>
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#include <dt-bindings/interrupt-controller/it8xxx2-wuc.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/i2c/it8xxx2-i2c.h>
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#include <dt-bindings/i2c/it8xxx2-i2c.h>
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#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
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#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
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@ -15,6 +16,7 @@
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#include <dt-bindings/pwm/it8xxx2_pwm.h>
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#include <dt-bindings/pwm/it8xxx2_pwm.h>
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#include <dt-bindings/sensor/it8xxx2_tach.h>
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#include <dt-bindings/sensor/it8xxx2_tach.h>
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#include "it8xxx2-alts-map.dtsi"
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#include "it8xxx2-alts-map.dtsi"
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#include "ite/it8xxx2-wuc-map.dtsi"
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/ {
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/ {
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#address-cells = <1>;
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#address-cells = <1>;
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@ -252,6 +254,167 @@
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compatible = "mmio-sram";
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compatible = "mmio-sram";
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reg = <0x80101000 DT_SIZE_K(56)>;
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reg = <0x80101000 DT_SIZE_K(56)>;
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};
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};
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wuc1: wakeup-controller@f01b00 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b00 1 /* WUEMR1 */
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0x00f01b04 1 /* WUESR1 */
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0x00f01b08 1 /* WUENR1 */
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0x00f01b3c 1>; /* WUBEMR1 */
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label = "WUC_1";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc2: wakeup-controller@f01b01 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b01 1 /* WUEMR2 */
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0x00f01b05 1 /* WUESR2 */
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IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */
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0x00f01b3d 1>; /* WUBEMR2 */
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label = "WUC_2";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc3: wakeup-controller@f01b02 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b02 1 /* WUEMR3 */
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0x00f01b06 1 /* WUESR3 */
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0x00f01b0a 1 /* WUENR3 */
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0x00f01b3e 1>; /* WUBEMR3 */
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label = "WUC_3";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc4: wakeup-controller@f01b03 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b03 1 /* WUEMR4 */
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0x00f01b07 1 /* WUESR4 */
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0x00f01b0b 1 /* WUENR4 */
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0x00f01b3f 1>; /* WUBEMR4 */
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label = "WUC_4";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc5: wakeup-controller@f01b0c {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b0c 1 /* WUEMR5 */
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0x00f01b0d 1 /* WUESR5 */
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IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */
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0x00f01b0f 1>; /* WUBEMR5 */
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label = "WUC_5";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc6: wakeup-controller@f01b10 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b10 1 /* WUEMR6 */
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0x00f01b11 1 /* WUESR6 */
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IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */
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0x00f01b13 1>; /* WUBEMR6 */
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label = "WUC_6";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc7: wakeup-controller@f01b14 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b14 1 /* WUEMR7 */
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0x00f01b15 1 /* WUESR7 */
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IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */
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0x00f01b17 1>; /* WUBEMR7 */
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label = "WUC_7";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc8: wakeup-controller@f01b18 {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b18 1 /* WUEMR8 */
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0x00f01b19 1 /* WUESR8 */
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IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */
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0x00f01b1b 1>; /* WUBEMR8 */
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label = "WUC_8";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc9: wakeup-controller@f01b1c {
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compatible = "ite,it8xxx2-wuc";
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reg = <0x00f01b1c 1 /* WUEMR9 */
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0x00f01b1d 1 /* WUESR9 */
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IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */
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0x00f01b1f 1>; /* WUBEMR9 */
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label = "WUC_9";
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wakeup-controller;
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#wuc-cells = <1>;
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};
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wuc10: wakeup-controller@f01b20 {
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||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b20 1 /* WUEMR10 */
|
||||||
|
0x00f01b21 1 /* WUESR10 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */
|
||||||
|
0x00f01b23 1>; /* WUBEMR10 */
|
||||||
|
label = "WUC_10";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
wuc11: wakeup-controller@f01b24 {
|
||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b24 1 /* WUEMR11 */
|
||||||
|
0x00f01b25 1 /* WUESR11 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */
|
||||||
|
0x00f01b27 1>; /* WUBEMR11 */
|
||||||
|
label = "WUC_11";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
wuc12: wakeup-controller@f01b28 {
|
||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b28 1 /* WUEMR12 */
|
||||||
|
0x00f01b29 1 /* WUESR12 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */
|
||||||
|
0x00f01b2b 1>; /* WUBEMR12 */
|
||||||
|
label = "WUC_12";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
wuc13: wakeup-controller@f01b2c {
|
||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b2c 1 /* WUEMR13 */
|
||||||
|
0x00f01b2d 1 /* WUESR13 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */
|
||||||
|
0x00f01b2f 1>; /* WUBEMR13 */
|
||||||
|
label = "WUC_13";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
wuc14: wakeup-controller@f01b30 {
|
||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b30 1 /* WUEMR14 */
|
||||||
|
0x00f01b31 1 /* WUESR14 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */
|
||||||
|
0x00f01b33 1>; /* WUBEMR14 */
|
||||||
|
label = "WUC_14";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
wuc15: wakeup-controller@f01b34 {
|
||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b34 1 /* WUEMR15 */
|
||||||
|
0x00f01b35 1 /* WUESR15 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */
|
||||||
|
0x00f01b37 1>; /* WUBEMR15 */
|
||||||
|
label = "WUC_15";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
wuc16: wakeup-controller@f01b38 {
|
||||||
|
compatible = "ite,it8xxx2-wuc";
|
||||||
|
reg = <0x00f01b38 1 /* WUEMR16 */
|
||||||
|
0x00f01b39 1 /* WUESR16 */
|
||||||
|
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */
|
||||||
|
0x00f01b3b 1>; /* WUBEMR16 */
|
||||||
|
label = "WUC_16";
|
||||||
|
wakeup-controller;
|
||||||
|
#wuc-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
intc: interrupt-controller@f03f00 {
|
intc: interrupt-controller@f03f00 {
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
compatible = "ite,it8xxx2-intc";
|
compatible = "ite,it8xxx2-intc";
|
||||||
|
|
|
||||||
377
dts/riscv/ite/it8xxx2-wuc-map.dtsi
Normal file
377
dts/riscv/ite/it8xxx2-wuc-map.dtsi
Normal file
|
|
@ -0,0 +1,377 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2022 ITE Corporation
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/dt-util.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
/* Mapping between wuc bits and source device */
|
||||||
|
it8xxx2-wuc-map {
|
||||||
|
compatible = "ite,it8xxx2-wuc-map";
|
||||||
|
|
||||||
|
/* WUC group 2 */
|
||||||
|
wuc_wu20: wu20 {
|
||||||
|
wucs = <&wuc2 BIT(0)>; /* GPD0 */
|
||||||
|
};
|
||||||
|
wuc_wu21: wu21 {
|
||||||
|
wucs = <&wuc2 BIT(1)>; /* GPD1 */
|
||||||
|
};
|
||||||
|
wuc_wu22: wu22 {
|
||||||
|
wucs = <&wuc2 BIT(2)>; /* GPC4 */
|
||||||
|
};
|
||||||
|
wuc_wu23: wu23 {
|
||||||
|
wucs = <&wuc2 BIT(3)>; /* GPC6 */
|
||||||
|
};
|
||||||
|
wuc_wu24: wu24{
|
||||||
|
wucs = <&wuc2 BIT(4)>; /* GPD2 */
|
||||||
|
};
|
||||||
|
wuc_wu25: wu25 {
|
||||||
|
wucs = <&wuc2 BIT(5)>; /* GPE4 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 3 */
|
||||||
|
wuc_wu30: wu30 {
|
||||||
|
wucs = <&wuc3 BIT(0)>; /* KSI[0] */
|
||||||
|
};
|
||||||
|
wuc_wu31: wu31 {
|
||||||
|
wucs = <&wuc3 BIT(1)>; /* KSI[1] */
|
||||||
|
};
|
||||||
|
wuc_wu32: wu32 {
|
||||||
|
wucs = <&wuc3 BIT(2)>; /* KSI[2] */
|
||||||
|
};
|
||||||
|
wuc_wu33: wu33 {
|
||||||
|
wucs = <&wuc3 BIT(3)>; /* KSI[3] */
|
||||||
|
};
|
||||||
|
wuc_wu34: wu34{
|
||||||
|
wucs = <&wuc3 BIT(4)>; /* KSI[4] */
|
||||||
|
};
|
||||||
|
wuc_wu35: wu35 {
|
||||||
|
wucs = <&wuc3 BIT(5)>; /* KSI[5] */
|
||||||
|
};
|
||||||
|
wuc_wu36: wu36 {
|
||||||
|
wucs = <&wuc3 BIT(6)>; /* KSI[6] */
|
||||||
|
};
|
||||||
|
wuc_wu37: wu37 {
|
||||||
|
wucs = <&wuc3 BIT(7)>; /* KSI[7] */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 4 */
|
||||||
|
wuc_wu40: wu40 {
|
||||||
|
wucs = <&wuc4 BIT(0)>; /* GPE5 */
|
||||||
|
};
|
||||||
|
wuc_wu45: wu45 {
|
||||||
|
wucs = <&wuc4 BIT(5)>; /* GPE6 */
|
||||||
|
};
|
||||||
|
wuc_wu46: wu46 {
|
||||||
|
wucs = <&wuc4 BIT(6)>; /* GPE7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 5 */
|
||||||
|
wuc_wu50: wu50 {
|
||||||
|
wucs = <&wuc5 BIT(0)>; /* GPK0 */
|
||||||
|
};
|
||||||
|
wuc_wu51: wu51 {
|
||||||
|
wucs = <&wuc5 BIT(1)>; /* GPK1 */
|
||||||
|
};
|
||||||
|
wuc_wu52: wu52 {
|
||||||
|
wucs = <&wuc5 BIT(2)>; /* GPK2 */
|
||||||
|
};
|
||||||
|
wuc_wu53: wu53 {
|
||||||
|
wucs = <&wuc5 BIT(3)>; /* GPK3 */
|
||||||
|
};
|
||||||
|
wuc_wu54: wu54 {
|
||||||
|
wucs = <&wuc5 BIT(4)>; /* GPK4 */
|
||||||
|
};
|
||||||
|
wuc_wu55: wu55 {
|
||||||
|
wucs = <&wuc5 BIT(5)>; /* GPK5 */
|
||||||
|
};
|
||||||
|
wuc_wu56: wu56 {
|
||||||
|
wucs = <&wuc5 BIT(6)>; /* GPK6 */
|
||||||
|
};
|
||||||
|
wuc_wu57: wu57 {
|
||||||
|
wucs = <&wuc5 BIT(7)>; /* GPK7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 6 */
|
||||||
|
wuc_wu60: wu60 {
|
||||||
|
wucs = <&wuc6 BIT(0)>; /* GPH0 */
|
||||||
|
};
|
||||||
|
wuc_wu61: wu61 {
|
||||||
|
wucs = <&wuc6 BIT(1)>; /* GPH1 */
|
||||||
|
};
|
||||||
|
wuc_wu62: wu62 {
|
||||||
|
wucs = <&wuc6 BIT(2)>; /* GPH2 */
|
||||||
|
};
|
||||||
|
wuc_wu63: wu63 {
|
||||||
|
wucs = <&wuc6 BIT(3)>; /* GPH3 */
|
||||||
|
};
|
||||||
|
wuc_wu64: wu64 {
|
||||||
|
wucs = <&wuc6 BIT(4)>; /* GPF4 */
|
||||||
|
};
|
||||||
|
wuc_wu65: wu65 {
|
||||||
|
wucs = <&wuc6 BIT(5)>; /* GPF5 */
|
||||||
|
};
|
||||||
|
wuc_wu66: wu66 {
|
||||||
|
wucs = <&wuc6 BIT(6)>; /* GPF6 */
|
||||||
|
};
|
||||||
|
wuc_wu67: wu67 {
|
||||||
|
wucs = <&wuc6 BIT(7)>; /* GPF7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 7 */
|
||||||
|
wuc_wu70: wu70 {
|
||||||
|
wucs = <&wuc7 BIT(0)>; /* GPE0 */
|
||||||
|
};
|
||||||
|
wuc_wu71: wu71 {
|
||||||
|
wucs = <&wuc7 BIT(1)>; /* GPE1 */
|
||||||
|
};
|
||||||
|
wuc_wu72: wu72 {
|
||||||
|
wucs = <&wuc7 BIT(2)>; /* GPE2 */
|
||||||
|
};
|
||||||
|
wuc_wu73: wu73 {
|
||||||
|
wucs = <&wuc7 BIT(3)>; /* GPE3 */
|
||||||
|
};
|
||||||
|
wuc_wu74: wu74 {
|
||||||
|
wucs = <&wuc7 BIT(4)>; /* GPI4 */
|
||||||
|
};
|
||||||
|
wuc_wu75: wu75 {
|
||||||
|
wucs = <&wuc7 BIT(5)>; /* GPI5 */
|
||||||
|
};
|
||||||
|
wuc_wu76: wu76 {
|
||||||
|
wucs = <&wuc7 BIT(6)>; /* GPI6 */
|
||||||
|
};
|
||||||
|
wuc_wu77: wu77 {
|
||||||
|
wucs = <&wuc7 BIT(7)>; /* GPI7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 8 */
|
||||||
|
wuc_wu80: wu80 {
|
||||||
|
wucs = <&wuc8 BIT(0)>; /* GPA3 */
|
||||||
|
};
|
||||||
|
wuc_wu81: wu81 {
|
||||||
|
wucs = <&wuc8 BIT(1)>; /* GPA4 */
|
||||||
|
};
|
||||||
|
wuc_wu82: wu82 {
|
||||||
|
wucs = <&wuc8 BIT(2)>; /* GPA5 */
|
||||||
|
};
|
||||||
|
wuc_wu83: wu83 {
|
||||||
|
wucs = <&wuc8 BIT(3)>; /* GPA6 */
|
||||||
|
};
|
||||||
|
wuc_wu84: wu84 {
|
||||||
|
wucs = <&wuc8 BIT(4)>; /* GPB2 */
|
||||||
|
};
|
||||||
|
wuc_wu85: wu85 {
|
||||||
|
wucs = <&wuc8 BIT(5)>; /* GPC0 */
|
||||||
|
};
|
||||||
|
wuc_wu86: wu86 {
|
||||||
|
wucs = <&wuc8 BIT(6)>; /* GPC7 */
|
||||||
|
};
|
||||||
|
wuc_wu87: wu87 {
|
||||||
|
wucs = <&wuc8 BIT(7)>; /* GPD7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 9 */
|
||||||
|
wuc_wu88: wu88 {
|
||||||
|
wucs = <&wuc9 BIT(0)>; /* GPH4 */
|
||||||
|
};
|
||||||
|
wuc_wu89: wu89 {
|
||||||
|
wucs = <&wuc9 BIT(1)>; /* GPH5 */
|
||||||
|
};
|
||||||
|
wuc_wu90: wu90 {
|
||||||
|
wucs = <&wuc9 BIT(2)>; /* GPH6 */
|
||||||
|
};
|
||||||
|
wuc_wu91: wu91 {
|
||||||
|
wucs = <&wuc9 BIT(3)>; /* GPA0 */
|
||||||
|
};
|
||||||
|
wuc_wu92: wu92 {
|
||||||
|
wucs = <&wuc9 BIT(4)>; /* GPA1 */
|
||||||
|
};
|
||||||
|
wuc_wu93: wu93 {
|
||||||
|
wucs = <&wuc9 BIT(5)>; /* GPA2 */
|
||||||
|
};
|
||||||
|
wuc_wu94: wu94 {
|
||||||
|
wucs = <&wuc9 BIT(6)>; /* GPB4 */
|
||||||
|
};
|
||||||
|
wuc_wu95: wu95 {
|
||||||
|
wucs = <&wuc9 BIT(7)>; /* GPC2 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 10 */
|
||||||
|
wuc_wu96: wu96 {
|
||||||
|
wucs = <&wuc10 BIT(0)>; /* GPF0 */
|
||||||
|
};
|
||||||
|
wuc_wu97: wu97 {
|
||||||
|
wucs = <&wuc10 BIT(1)>; /* GPF1 */
|
||||||
|
};
|
||||||
|
wuc_wu98: wu98 {
|
||||||
|
wucs = <&wuc10 BIT(2)>; /* GPF2 */
|
||||||
|
};
|
||||||
|
wuc_wu99: wu99 {
|
||||||
|
wucs = <&wuc10 BIT(3)>; /* GPF3 */
|
||||||
|
};
|
||||||
|
wuc_wu100: wu100 {
|
||||||
|
wucs = <&wuc10 BIT(4)>; /* GPA7 */
|
||||||
|
};
|
||||||
|
wuc_wu101: wu101 {
|
||||||
|
wucs = <&wuc10 BIT(5)>; /* GPB0 */
|
||||||
|
};
|
||||||
|
wuc_wu102: wu102 {
|
||||||
|
wucs = <&wuc10 BIT(6)>; /* GPB1 */
|
||||||
|
};
|
||||||
|
wuc_wu103: wu103 {
|
||||||
|
wucs = <&wuc10 BIT(7)>; /* GPB3 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 11 */
|
||||||
|
wuc_wu104: wu104 {
|
||||||
|
wucs = <&wuc11 BIT(0)>; /* GPB5 */
|
||||||
|
};
|
||||||
|
wuc_wu105: wu105 {
|
||||||
|
wucs = <&wuc11 BIT(1)>; /* GPB6 */
|
||||||
|
};
|
||||||
|
wuc_wu106: wu106 {
|
||||||
|
wucs = <&wuc11 BIT(2)>; /* GPB7 */
|
||||||
|
};
|
||||||
|
wuc_wu107: wu107 {
|
||||||
|
wucs = <&wuc11 BIT(3)>; /* GPC1 */
|
||||||
|
};
|
||||||
|
wuc_wu108: wu108 {
|
||||||
|
wucs = <&wuc11 BIT(4)>; /* GPC3 */
|
||||||
|
};
|
||||||
|
wuc_wu109: wu109 {
|
||||||
|
wucs = <&wuc11 BIT(5)>; /* GPC5 */
|
||||||
|
};
|
||||||
|
wuc_wu110: wu110 {
|
||||||
|
wucs = <&wuc11 BIT(6)>; /* GPD3 */
|
||||||
|
};
|
||||||
|
wuc_wu111: wu111 {
|
||||||
|
wucs = <&wuc11 BIT(7)>; /* GPD4 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 12 */
|
||||||
|
wuc_wu112: wu112 {
|
||||||
|
wucs = <&wuc12 BIT(0)>; /* GPD5 */
|
||||||
|
};
|
||||||
|
wuc_wu113: wu113 {
|
||||||
|
wucs = <&wuc12 BIT(1)>; /* GPD6 */
|
||||||
|
};
|
||||||
|
wuc_wu114: wu114 {
|
||||||
|
wucs = <&wuc12 BIT(2)>; /* GPE4 */
|
||||||
|
};
|
||||||
|
wuc_wu115: wu115 {
|
||||||
|
wucs = <&wuc12 BIT(3)>; /* GPG0 */
|
||||||
|
};
|
||||||
|
wuc_wu116: wu116 {
|
||||||
|
wucs = <&wuc12 BIT(4)>; /* GPG1 */
|
||||||
|
};
|
||||||
|
wuc_wu117: wu117 {
|
||||||
|
wucs = <&wuc12 BIT(5)>; /* GPG2 */
|
||||||
|
};
|
||||||
|
wuc_wu118: wu118 {
|
||||||
|
wucs = <&wuc12 BIT(6)>; /* GPG6 */
|
||||||
|
};
|
||||||
|
wuc_wu119: wu119 {
|
||||||
|
wucs = <&wuc12 BIT(7)>; /* GPI0 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 13 */
|
||||||
|
wuc_wu120: wu120 {
|
||||||
|
wucs = <&wuc13 BIT(0)>; /* GPI1 */
|
||||||
|
};
|
||||||
|
wuc_wu121: wu121 {
|
||||||
|
wucs = <&wuc13 BIT(1)>; /* GPI2 */
|
||||||
|
};
|
||||||
|
wuc_wu122: wu122 {
|
||||||
|
wucs = <&wuc13 BIT(2)>; /* GPI3 */
|
||||||
|
};
|
||||||
|
wuc_wu123: wu123 {
|
||||||
|
wucs = <&wuc13 BIT(3)>; /* GPG3 */
|
||||||
|
};
|
||||||
|
wuc_wu124: wu124 {
|
||||||
|
wucs = <&wuc13 BIT(4)>; /* GPG4 */
|
||||||
|
};
|
||||||
|
wuc_wu125: wu125 {
|
||||||
|
wucs = <&wuc13 BIT(5)>; /* GPG5 */
|
||||||
|
};
|
||||||
|
wuc_wu126: wu126 {
|
||||||
|
wucs = <&wuc13 BIT(6)>; /* GPG7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 14 */
|
||||||
|
wuc_wu128: wu128 {
|
||||||
|
wucs = <&wuc14 BIT(0)>; /* GPJ0 */
|
||||||
|
};
|
||||||
|
wuc_wu129: wu129 {
|
||||||
|
wucs = <&wuc14 BIT(1)>; /* GPJ1 */
|
||||||
|
};
|
||||||
|
wuc_wu130: wu130 {
|
||||||
|
wucs = <&wuc14 BIT(2)>; /* GPJ2 */
|
||||||
|
};
|
||||||
|
wuc_wu131: wu131 {
|
||||||
|
wucs = <&wuc14 BIT(3)>; /* GPJ3 */
|
||||||
|
};
|
||||||
|
wuc_wu132: wu132 {
|
||||||
|
wucs = <&wuc14 BIT(4)>; /* GPJ4 */
|
||||||
|
};
|
||||||
|
wuc_wu133: wu133 {
|
||||||
|
wucs = <&wuc14 BIT(5)>; /* GPJ5 */
|
||||||
|
};
|
||||||
|
wuc_wu134: wu134 {
|
||||||
|
wucs = <&wuc14 BIT(6)>; /* GPJ6 */
|
||||||
|
};
|
||||||
|
wuc_wu135: wu135 {
|
||||||
|
wucs = <&wuc14 BIT(7)>; /* GPJ7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 15 */
|
||||||
|
wuc_wu136: wu136 {
|
||||||
|
wucs = <&wuc15 BIT(0)>; /* GPIO L0 */
|
||||||
|
};
|
||||||
|
wuc_wu137: wu137 {
|
||||||
|
wucs = <&wuc15 BIT(1)>; /* GPIO L1 */
|
||||||
|
};
|
||||||
|
wuc_wu138: wu138 {
|
||||||
|
wucs = <&wuc15 BIT(2)>; /* GPIO L2 */
|
||||||
|
};
|
||||||
|
wuc_wu139: wu139 {
|
||||||
|
wucs = <&wuc15 BIT(3)>; /* GPIO L3 */
|
||||||
|
};
|
||||||
|
wuc_wu140: wu140 {
|
||||||
|
wucs = <&wuc15 BIT(4)>; /* GPIO L4 */
|
||||||
|
};
|
||||||
|
wuc_wu141: wu141 {
|
||||||
|
wucs = <&wuc15 BIT(5)>; /* GPIO L5 */
|
||||||
|
};
|
||||||
|
wuc_wu142: wu142 {
|
||||||
|
wucs = <&wuc15 BIT(6)>; /* GPIO L6 */
|
||||||
|
};
|
||||||
|
wuc_wu143: wu143 {
|
||||||
|
wucs = <&wuc15 BIT(7)>; /* GPIO L7 */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* WUC group 16 */
|
||||||
|
wuc_wu144: wu144 {
|
||||||
|
wucs = <&wuc16 BIT(0)>; /* GPM0 */
|
||||||
|
};
|
||||||
|
wuc_wu145: wu145 {
|
||||||
|
wucs = <&wuc16 BIT(1)>; /* GPM1 */
|
||||||
|
};
|
||||||
|
wuc_wu146: wu146 {
|
||||||
|
wucs = <&wuc16 BIT(2)>; /* GPM2 */
|
||||||
|
};
|
||||||
|
wuc_wu147: wu147 {
|
||||||
|
wucs = <&wuc16 BIT(3)>; /* GPM3 */
|
||||||
|
};
|
||||||
|
wuc_wu148: wu148 {
|
||||||
|
wucs = <&wuc16 BIT(4)>; /* GPM4 */
|
||||||
|
};
|
||||||
|
wuc_wu149: wu149 {
|
||||||
|
wucs = <&wuc16 BIT(5)>; /* GPM5 */
|
||||||
|
};
|
||||||
|
wuc_wu150: wu150 {
|
||||||
|
wucs = <&wuc16 BIT(6)>; /* GPM6 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
50
include/drivers/interrupt_controller/wuc_ite_it8xxx2.h
Normal file
50
include/drivers/interrupt_controller/wuc_ite_it8xxx2.h
Normal file
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 ITE Corporation. All Rights Reserved
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_
|
||||||
|
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_
|
||||||
|
|
||||||
|
#include <device.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief A trigger condition on the corresponding input generates
|
||||||
|
* a wake-up signal to the power management control of EC
|
||||||
|
*
|
||||||
|
* @param dev Pointer to the device structure for the driver instance
|
||||||
|
* @param mask Pin mask of WUC group
|
||||||
|
*/
|
||||||
|
void it8xxx2_wuc_enable(const struct device *dev, uint8_t mask);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief A trigger condition on the corresponding input doesn't
|
||||||
|
* assert the wake-up signal (canceled not pending)
|
||||||
|
*
|
||||||
|
* @param dev Pointer to the device structure for the driver instance
|
||||||
|
* @param mask Pin mask of WUC group
|
||||||
|
*/
|
||||||
|
void it8xxx2_wuc_disable(const struct device *dev, uint8_t mask);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write-1-clear a trigger condition that occurs on the
|
||||||
|
* corresponding input
|
||||||
|
*
|
||||||
|
* @param dev Pointer to the device structure for the driver instance
|
||||||
|
* @param mask Pin mask of WUC group
|
||||||
|
*/
|
||||||
|
void it8xxx2_wuc_clear_status(const struct device *dev, uint8_t mask);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select the trigger edge mode on the corresponding input
|
||||||
|
*
|
||||||
|
* @param dev Pointer to the device structure for the driver instance
|
||||||
|
* @param mask Pin mask of WUC group
|
||||||
|
* @param flags Select the trigger edge mode
|
||||||
|
*/
|
||||||
|
void it8xxx2_wuc_set_polarity(const struct device *dev, uint8_t mask,
|
||||||
|
uint32_t flags);
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_ */
|
||||||
28
include/dt-bindings/interrupt-controller/it8xxx2-wuc.h
Normal file
28
include/dt-bindings/interrupt-controller/it8xxx2-wuc.h
Normal file
|
|
@ -0,0 +1,28 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_
|
||||||
|
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_
|
||||||
|
|
||||||
|
#include <dt-bindings/dt-util.h>
|
||||||
|
|
||||||
|
/** WUC reserved register of reg property */
|
||||||
|
#define IT8XXX2_WUC_UNUSED_REG 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name wakeup controller flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** WUC rising edge trigger mode */
|
||||||
|
#define WUC_TYPE_EDGE_RISING BIT(0)
|
||||||
|
/** WUC falling edge trigger mode */
|
||||||
|
#define WUC_TYPE_EDGE_FALLING BIT(1)
|
||||||
|
/** WUC both edge trigger mode */
|
||||||
|
#define WUC_TYPE_EDGE_BOTH (WUC_TYPE_EDGE_RISING | WUC_TYPE_EDGE_FALLING)
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_ */
|
||||||
|
|
@ -41,4 +41,60 @@
|
||||||
inst) \
|
inst) \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For it8xxx2 wake-up controller (WUC)
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DEV_WUC(idx, inst) \
|
||||||
|
DEVICE_DT_GET(DT_PHANDLE(IT8XXX2_DT_INST_WUCCTRL(inst, idx), wucs))
|
||||||
|
#define IT8XXX2_DEV_WUC_MASK(idx, inst) \
|
||||||
|
DT_PHA(IT8XXX2_DT_INST_WUCCTRL(inst, idx), wucs, mask)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief For it8xxx2, get a node identifier from a wucctrl property
|
||||||
|
* for a DT_DRV_COMPAT instance
|
||||||
|
*
|
||||||
|
* @param inst instance number
|
||||||
|
* @param idx index in the wucctrl property
|
||||||
|
* @return node identifier for the phandle at index idx in the wucctrl
|
||||||
|
* property of that DT_DRV_COMPAT instance
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_INST_WUCCTRL(inst, idx) \
|
||||||
|
DT_INST_PHANDLE_BY_IDX(inst, wucctrl, idx)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief For it8xxx2, construct wuc map structure in LISTIFY extension
|
||||||
|
*
|
||||||
|
* @param idx index in LISTIFY extension
|
||||||
|
* @param inst instance number for compatible defined in DT_DRV_COMPAT
|
||||||
|
* @return a structure of *_wuc_map_cfg
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_WUC_ITEMS_FUNC(idx, inst) \
|
||||||
|
{ \
|
||||||
|
.wucs = IT8XXX2_DEV_WUC(idx, inst), \
|
||||||
|
.mask = IT8XXX2_DEV_WUC_MASK(idx, inst), \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief For it8xxx2, get the length of wucctrl property which
|
||||||
|
* type is 'phandle-array' for a DT_DRV_COMPAT instance
|
||||||
|
*
|
||||||
|
* @param inst instance number
|
||||||
|
* @return length of wucctrl property which type is 'phandle-array'
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_INST_WUCCTRL_LEN(inst) \
|
||||||
|
DT_INST_PROP_LEN(inst, wucctrl)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief For it8xxx2, construct an array of it8xxx2 wuc map structure
|
||||||
|
* with compatible defined in DT_DRV_COMPAT by LISTIFY func
|
||||||
|
*
|
||||||
|
* @param inst instance number for compatible defined in DT_DRV_COMPAT
|
||||||
|
* @return an array of *_wuc_map_cfg structure
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_WUC_ITEMS_LIST(inst) { \
|
||||||
|
LISTIFY(IT8XXX2_DT_INST_WUCCTRL_LEN(inst), \
|
||||||
|
IT8XXX2_DT_WUC_ITEMS_FUNC, (,), \
|
||||||
|
inst) \
|
||||||
|
}
|
||||||
|
|
||||||
#endif /* _ITE_IT8XXX2_SOC_DT_H_ */
|
#endif /* _ITE_IT8XXX2_SOC_DT_H_ */
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue