i2c/i2c_quark_se_ss: convert to using static IRQ API
This converts the i2c_quark_se_ss to use the static IRQ API. Note that, even with separate config functions for each instance of the driver, it is still saving both RAM and ROM space. Change-Id: Ieb555ff281b384d87d8e69f6914878bbee0e2ee9 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
a704277193
commit
4b2a576c80
3 changed files with 95 additions and 88 deletions
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@ -642,63 +642,15 @@ int i2c_qse_ss_initialize(struct device *dev)
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return DEV_OK;
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}
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void _i2c_qse_ss_config_irq(struct device *port)
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{
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struct i2c_qse_ss_rom_config * const rom = port->config->config_info;
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uint32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, rom->isr_err_mask);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, rom->isr_err_mask, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, rom->isr_tx_mask);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, rom->isr_tx_mask, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, rom->isr_rx_mask);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, rom->isr_rx_mask, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, rom->isr_stop_mask);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, rom->isr_stop_mask, mask);
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/* Connect the IRQs to ISR */
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irq_connect_dynamic(rom->isr_err_vector, 1, i2c_qse_ss_isr, port, 0);
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irq_connect_dynamic(rom->isr_rx_vector, 1, i2c_qse_ss_isr, port, 0);
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irq_connect_dynamic(rom->isr_tx_vector, 1, i2c_qse_ss_isr, port, 0);
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irq_connect_dynamic(rom->isr_stop_vector, 1, i2c_qse_ss_isr, port, 0);
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irq_enable(rom->isr_err_vector);
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irq_enable(rom->isr_rx_vector);
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irq_enable(rom->isr_tx_vector);
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irq_enable(rom->isr_stop_vector);
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}
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#if CONFIG_I2C_QUARK_SE_SS_0
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#include <init.h>
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void _i2c_qse_ss_config_irq_0(struct device *port);
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struct i2c_qse_ss_rom_config i2c_config_ss_0 = {
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.base_address = CONFIG_I2C_QUARK_SE_SS_0_BASE,
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.config_func = _i2c_qse_ss_config_irq,
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.isr_err_vector = I2C_SS_0_ERR_VECTOR,
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.isr_err_mask = I2C_SS_0_ERR_MASK,
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.isr_rx_vector = I2C_SS_0_RX_VECTOR,
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.isr_rx_mask = I2C_SS_0_RX_MASK,
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.isr_tx_vector = I2C_SS_0_TX_VECTOR,
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.isr_tx_mask = I2C_SS_0_TX_MASK,
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.isr_stop_vector = I2C_SS_0_STOP_VECTOR,
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.isr_stop_mask = I2C_SS_0_STOP_MASK,
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.config_func = _i2c_qse_ss_config_irq_0,
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};
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struct i2c_qse_ss_dev_config i2c_ss_0_runtime = {
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@ -713,27 +665,57 @@ DECLARE_DEVICE_INIT_CONFIG(i2c_ss_0,
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SYS_DEFINE_DEVICE(i2c_ss_0, &i2c_ss_0_runtime,
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SECONDARY, CONFIG_I2C_INIT_PRIORITY);
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void _i2c_qse_ss_config_irq_0(struct device *port)
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{
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uint32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_0_ERR_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_0_ERR_MASK, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_0_TX_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_0_TX_MASK, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_0_RX_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_0_RX_MASK, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_0_STOP_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_0_STOP_MASK, mask);
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/* Connect the IRQs to ISR */
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irq_connect(I2C_SS_0_ERR_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_0), 0);
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irq_connect(I2C_SS_0_RX_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_0), 0);
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irq_connect(I2C_SS_0_TX_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_0), 0);
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irq_connect(I2C_SS_0_STOP_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_0), 0);
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irq_enable(I2C_SS_0_ERR_VECTOR);
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irq_enable(I2C_SS_0_RX_VECTOR);
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irq_enable(I2C_SS_0_TX_VECTOR);
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irq_enable(I2C_SS_0_STOP_VECTOR);
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}
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#endif /* CONFIG_I2C_QUARK_SE_SS_0 */
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#if CONFIG_I2C_QUARK_SE_SS_1
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#include <init.h>
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void _i2c_qse_ss_config_irq_1(struct device *port);
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struct i2c_qse_ss_rom_config i2c_config_ss_1 = {
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.base_address = CONFIG_I2C_QUARK_SE_SS_1_BASE,
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.config_func = _i2c_qse_ss_config_irq,
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.isr_err_vector = I2C_SS_1_ERR_VECTOR,
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.isr_err_mask = I2C_SS_1_ERR_MASK,
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.isr_rx_vector = I2C_SS_1_RX_VECTOR,
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.isr_rx_mask = I2C_SS_1_RX_MASK,
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.isr_tx_vector = I2C_SS_1_TX_VECTOR,
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.isr_tx_mask = I2C_SS_1_TX_MASK,
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.isr_stop_vector = I2C_SS_1_STOP_VECTOR,
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.isr_stop_mask = I2C_SS_1_STOP_MASK,
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.config_func = _i2c_qse_ss_config_irq_1,
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};
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struct i2c_qse_ss_dev_config i2c_qse_ss_1_runtime = {
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@ -748,4 +730,45 @@ DECLARE_DEVICE_INIT_CONFIG(i2c_ss_1,
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SYS_DEFINE_DEVICE(i2c_ss_1, &i2c_qse_ss_1_runtime,
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SECONDARY, CONFIG_I2C_INIT_PRIORITY);
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void _i2c_qse_ss_config_irq_1(struct device *port)
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{
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uint32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_1_ERR_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_1_ERR_MASK, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_1_TX_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_1_TX_MASK, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_1_RX_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_1_RX_MASK, mask);
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mask = _i2c_qse_ss_memory_read(SCSS_REGISTER_BASE, I2C_SS_1_STOP_MASK);
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mask &= INT_ENABLE_ARC;
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_i2c_qse_ss_memory_write(SCSS_REGISTER_BASE, I2C_SS_1_STOP_MASK, mask);
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/* Connect the IRQs to ISR */
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irq_connect(I2C_SS_1_ERR_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_1), 0);
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irq_connect(I2C_SS_1_RX_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_1), 0);
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irq_connect(I2C_SS_1_TX_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_1), 0);
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irq_connect(I2C_SS_1_STOP_VECTOR, 1, i2c_qse_ss_isr,
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SYS_GET_DEVICE(i2c_ss_1), 0);
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irq_enable(I2C_SS_1_ERR_VECTOR);
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irq_enable(I2C_SS_1_RX_VECTOR);
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irq_enable(I2C_SS_1_TX_VECTOR);
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irq_enable(I2C_SS_1_STOP_VECTOR);
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}
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#endif /* CONFIG_I2C_QUARK_SE_SS_1 */
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@ -54,22 +54,6 @@ struct i2c_qse_ss_rom_config {
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uint32_t base_address;
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i2c_qse_ss_cfg_func_t config_func;
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/* IRQ for ERR (error) conditions */
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uint32_t isr_err_vector;
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uint32_t isr_err_mask;
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/* IRQ for RX_AVAIL */
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uint32_t isr_rx_vector;
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uint32_t isr_rx_mask;
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/* IRQ for TX_REQ */
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uint32_t isr_tx_vector;
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uint32_t isr_tx_mask;
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/* IRQ for STOP_DET */
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uint32_t isr_stop_vector;
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uint32_t isr_stop_mask;
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};
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struct i2c_qse_ss_dev_config {
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