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cmake: xtensa: update xtensa SoC to use SOC_LINKER_SCRIPT variable

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This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen 2023-10-27 21:46:21 +02:00 • committed by Carles Cufí
commit 4b02bbc329
15 changed files with 31 additions and 104 deletions
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2
soc/xtensa/dc233c/CMakeLists.txt
View file

@ -1,3 +1,5 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU mmu.c)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-dc233c.ld CACHE INTERNAL "")

12
soc/xtensa/dc233c/linker.ld
View file

@ -1,12 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#include <xtensa-dc233c.ld>

6
soc/xtensa/espressif_esp32/esp32/CMakeLists.txt
View file

@ -95,3 +95,9 @@ endif()
board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
if(CONFIG_MCUBOOT)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
else()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
endif()

20
soc/xtensa/espressif_esp32/esp32/linker.ld
View file

@ -1,20 +0,0 @@
/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
*/
#if defined(CONFIG_MCUBOOT)
/* Using mcuboot as ESP32 2nd stage bootloader */
#include "mcuboot.ld"
#else
/* Application default linker script */
#include "default.ld"
#endif /* CONFIG_MCUBOOT */

2
soc/xtensa/espressif_esp32/esp32_net/CMakeLists.txt
View file

@ -19,3 +19,5 @@ if(CONFIG_BUILD_OUTPUT_BIN)
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c
-a "esp32_net_fw_array")
endif()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

6
soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt
View file

@ -93,3 +93,9 @@ endif()
board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
if(CONFIG_MCUBOOT)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
else()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
endif()

20
soc/xtensa/espressif_esp32/esp32s2/linker.ld
View file

@ -1,20 +0,0 @@
/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
*/
#if defined(CONFIG_MCUBOOT)
/* Using mcuboot as ESP32S2 2nd stage bootloader */
#include "mcuboot.ld"
#else
/* Application default linker script */
#include "default.ld"
#endif /* CONFIG_MCUBOOT */

8
soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt
View file

@ -112,3 +112,11 @@ else()
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
endif()
if(CONFIG_MCUBOOT)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
elseif(CONFIG_SOC_ESP32S3_APPCPU)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "")
else()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
endif()

25
soc/xtensa/espressif_esp32/esp32s3/linker.ld
View file

@ -1,25 +0,0 @@
/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
*/
#if defined(CONFIG_MCUBOOT)
/* Using mcuboot as ESP32S3 2nd stage bootloader */
#include "mcuboot.ld"
#else
/* Application default linker script */
#if defined(CONFIG_SOC_ESP32S3_APPCPU)
#include "default_appcpu.ld"
#else
#include "default.ld"
#endif
#endif /* CONFIG_MCUBOOT */

2
soc/xtensa/intel_adsp/ace/CMakeLists.txt
View file

@ -15,3 +15,5 @@ zephyr_library_sources(
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

2
soc/xtensa/intel_adsp/cavs/CMakeLists.txt
View file

@ -17,3 +17,5 @@ if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1)
endif()
zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL irq.c)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-cavs-linker.ld CACHE INTERNAL "")

14
soc/xtensa/intel_adsp/cavs/linker.ld
View file

@ -1,14 +0,0 @@
/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the intel_apl_adsp platform
*/
#include <xtensa-cavs-linker.ld>

2
soc/xtensa/nxp_adsp/CMakeLists.txt
View file

@ -22,3 +22,5 @@ add_custom_command(
COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/${SOC_SERIES}/linker.ld CACHE INTERNAL "")

2
soc/xtensa/sample_controller/CMakeLists.txt
View file

@ -1,3 +1,3 @@
# SPDX-License-Identifier: Apache-2.0
# intentionally left empty
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-sample-controller.ld CACHE INTERNAL "")

12
soc/xtensa/sample_controller/linker.ld
View file

@ -1,12 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#include <xtensa-sample-controller.ld>