riscv32: added support for the SiFive Freedom E310 SOC

The SiFive Freedom E310 SOC follows the riscv privilege
architecture specification and hence is declared within
the riscv privilege SOC family.

It also provides support for a riscv
Platform Level Interrupt Controller (PLIC)

Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>

include/arch/riscv32/arch.h

@@ -127,6 +127,8 @@ extern uint32_t _timer_cycle_get_32(void);
 #include <arch/riscv32/pulpino/asm_inline.h>
 #elif defined(CONFIG_SOC_RISCV32_QEMU)
 #include <arch/riscv32/riscv32-qemu/asm_inline.h>
+#elif defined(CONFIG_SOC_RISCV32_FE310)
+#include <arch/riscv32/fe310/asm_inline.h>
 #endif
 
 #ifdef __cplusplus

include/arch/riscv32/fe310/asm_inline.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ASM_INLINE_PUBLIC_H
+#define _ASM_INLINE_PUBLIC_H
+
+/*
+ * The file must not be included directly
+ * Include arch/cpu.h instead
+ */
+
+#if defined(__GNUC__)
+#include <arch/riscv32/fe310/asm_inline_gcc.h>
+#else
+#error "Supports only GNU C compiler"
+#endif
+
+#endif /* _ASM_INLINE_PUBLIC_H */

include/arch/riscv32/fe310/asm_inline_gcc.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ASM_INLINE_GCC_H
+#define _ASM_INLINE_GCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * The file must not be included directly
+ * Include arch/cpu.h instead
+ * TEMPORARY
+ */
+
+#ifndef _ASMLANGUAGE
+
+#include <toolchain.h>
+
+/**
+ *
+ * @brief find least significant bit set in a 32-bit word
+ *
+ * This routine finds the first bit set starting from the least significant bit
+ * in the argument passed in and returns the index of that bit.  Bits are
+ * numbered starting at 1 from the least significant bit.  A return value of
+ * zero indicates that the value passed is zero.
+ *
+ * @return least significant bit set, 0 if @a op is 0
+ */
+static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
+{
+	return __builtin_ffs(op);
+}
+
+/**
+ *
+ * @brief find most significant bit set in a 32-bit word
+ *
+ * This routine finds the first bit set starting from the most significant bit
+ * in the argument passed in and returns the index of that bit.  Bits are
+ * numbered starting at 1 from the least significant bit.  A return value of
+ * zero indicates that the value passed is zero.
+ *
+ * @return most significant bit set, 0 if @a op is 0
+ */
+static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
+{
+	if (!op)
+		return 0;
+
+	return 32 - __builtin_clz(op);
+}
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASM_INLINE_GCC_PUBLIC_GCC_H */