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drivers: esp32/clock_control: Add Clock Driver

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- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).

- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node

Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
This commit is contained in:
Mohamed ElShahawi 2020-05-23 15:46:29 +02:00 • committed by Kumar Gala
commit 4acac3e9ef
15 changed files with 550 additions and 2 deletions
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2
soc/xtensa/esp32/Kconfig.soc
View file

@ -4,3 +4,5 @@
config SOC_ESP32
bool "ESP32"
select XTENSA
select CLOCK_CONTROL
select CLOCK_CONTROL_ESP32

3
soc/xtensa/esp32/linker.ld
View file

@ -25,12 +25,15 @@ PROVIDE ( __stack = 0x3ffe3f20 );
PROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );
PROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );
PROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );
PROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );
PROVIDE ( esp32_rom_intr_matrix_set = 0x4000681c );
PROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );
PROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );
PROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );
PROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );
PROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );
PROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );
PROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );
MEMORY
{

5
soc/xtensa/esp32/soc.h
View file

@ -52,6 +52,7 @@ extern int esp32_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
bool out_enabled_inverted);
extern void esp32_rom_uart_attach(void);
extern void esp32_rom_uart_tx_wait_idle(uint8_t uart_no);
extern STATUS esp32_rom_uart_tx_one_char(uint8_t chr);
extern STATUS esp32_rom_uart_rx_one_char(uint8_t *chr);
@ -59,4 +60,8 @@ extern void esp32_rom_Cache_Flush(int cpu);
extern void esp32_rom_Cache_Read_Enable(int cpu);
extern void esp32_rom_ets_set_appcpu_boot_addr(void *addr);
/* ROM functions which read/write internal i2c control bus for PLL, APLL */
extern uint8_t esp32_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
extern void esp32_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
#endif /* __SOC_H__ */