soc: arm: atmel: Add sam4e mcu
Add sam4e related soc files. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
parent
527ebe131d
commit
4a5de7bb87
9 changed files with 564 additions and 0 deletions
5
soc/arm/atmel_sam/sam4e/CMakeLists.txt
Normal file
5
soc/arm/atmel_sam/sam4e/CMakeLists.txt
Normal file
|
@ -0,0 +1,5 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
29
soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series
Normal file
29
soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series
Normal file
|
@ -0,0 +1,29 @@
|
|||
# Atmel SAM4E MCU series configuration options
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2019 Gerson Fernando Budke
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_SERIES
|
||||
default "sam4e"
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "sam4e16e" if SOC_PART_NUMBER_SAM4E16E
|
||||
default "sam4e16c" if SOC_PART_NUMBER_SAM4E16C
|
||||
default "sam4e8e" if SOC_PART_NUMBER_SAM4E8E
|
||||
default "sam4e8c" if SOC_PART_NUMBER_SAM4E8C
|
||||
|
||||
#
|
||||
# SAM4E family has total 47 peripherals capable of
|
||||
# generating interrupts.
|
||||
#
|
||||
config NUM_IRQS
|
||||
default 47
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 120000000
|
||||
|
||||
endif # SOC_SERIES_SAM4E
|
16
soc/arm/atmel_sam/sam4e/Kconfig.series
Normal file
16
soc/arm/atmel_sam/sam4e/Kconfig.series
Normal file
|
@ -0,0 +1,16 @@
|
|||
# Atmel SAM4E MCU series
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2019 Gerson Fernando Budke
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4E
|
||||
bool "Atmel SAM4E MCU"
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select SOC_FAMILY_SAM
|
||||
select ASF
|
||||
help
|
||||
Enable support for Atmel SAM4E Cortex-M4 microcontrollers.
|
||||
Part No.: SAM4E16E, SAM4E16C, SAM4E8E, SAM4E8C
|
91
soc/arm/atmel_sam/sam4e/Kconfig.soc
Normal file
91
soc/arm/atmel_sam/sam4e/Kconfig.soc
Normal file
|
@ -0,0 +1,91 @@
|
|||
# Atmel SAM4E MCU series
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2019 Gerson Fernando Budke
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
choice
|
||||
prompt "Atmel SAM4E MCU Selection"
|
||||
depends on SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_PART_NUMBER_SAM4E16E
|
||||
bool "SAM4E16E"
|
||||
|
||||
config SOC_PART_NUMBER_SAM4E16C
|
||||
bool "SAM4E16C"
|
||||
|
||||
config SOC_PART_NUMBER_SAM4E8E
|
||||
bool "SAM4E8E"
|
||||
|
||||
config SOC_PART_NUMBER_SAM4E8C
|
||||
bool "SAM4E8C"
|
||||
|
||||
endchoice
|
||||
|
||||
if SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_ATMEL_SAM4E_EXT_SLCK
|
||||
bool "Atmel SAM4E to use external crystal oscillator for slow clock"
|
||||
help
|
||||
Says y if you want to use external 32 kHz crystal
|
||||
oscillator to drive the slow clock. Note that this
|
||||
adds a few seconds to boot time, as the crystal
|
||||
needs to stabilize after power-up.
|
||||
|
||||
Says n if you do not need accurate and precise timers.
|
||||
The slow clock will be driven by the internal fast
|
||||
RC oscillator running at 32 kHz.
|
||||
|
||||
config SOC_ATMEL_SAM4E_EXT_MAINCK
|
||||
bool "Atmel SAM4E to use external crystal oscillator for main clock"
|
||||
help
|
||||
The main clock is being used to drive the PLL, and
|
||||
thus driving the processor clock.
|
||||
|
||||
Says y if you want to use external crystal oscillator
|
||||
to drive the main clock. Note that this adds about
|
||||
a second to boot time, as the crystal needs to
|
||||
stabilize after power-up.
|
||||
|
||||
The crystal used here can be from 3 to 20 MHz.
|
||||
|
||||
Says n here will use the internal fast RC oscillator
|
||||
running at 12 MHz.
|
||||
|
||||
config SOC_ATMEL_SAM4E_PLLA_MULA
|
||||
hex "PLL MULA"
|
||||
default 0x09
|
||||
help
|
||||
This is the multiplier (MULA) used by the PLL.
|
||||
The processor clock is (MAINCK * (MULA + 1) / DIVA).
|
||||
|
||||
Board config file can override this settings
|
||||
for a particular board.
|
||||
|
||||
With default of MULA == 9, and DIVA == 1,
|
||||
PLL is running at 10 times of main clock.
|
||||
|
||||
config SOC_ATMEL_SAM4E_PLLA_DIVA
|
||||
hex "PLL DIVA"
|
||||
default 0x01
|
||||
help
|
||||
This is the divider (DIVA) used by the PLL.
|
||||
The processor clock is (MAINCK * (MULA + 1) / DIVA).
|
||||
|
||||
Board config file can override this settings
|
||||
for a particular board.
|
||||
|
||||
With default of MULA == 9, and DIVA == 1,
|
||||
PLL is running at 10 times of main clock.
|
||||
|
||||
config SOC_ATMEL_SAM4E_WAIT_MODE
|
||||
bool "Atmel SAM4E goes to Wait mode instead of Sleep mode"
|
||||
depends on SOC_ATMEL_SAM4E_EXT_MAINCK
|
||||
default y if DEBUG
|
||||
help
|
||||
For JTAG debugging CPU clock (HCLK) should not stop. In order
|
||||
to achieve this, make CPU go to Wait mode instead of Sleep
|
||||
mode while using external crystal oscillator for main clock.
|
||||
|
||||
endif # SOC_SERIES_SAM4E
|
78
soc/arm/atmel_sam/sam4e/dts_fixup.h
Normal file
78
soc/arm/atmel_sam/sam4e/dts_fixup.h
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Gerson Fernando Budke
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* This file is a temporary workaround for mapping of the generated
|
||||
* information to the current driver definitions. This will be removed
|
||||
* when the drivers are modified to handle the generated information,
|
||||
* or the mapping of generated data matches the driver definitions.
|
||||
*/
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL
|
||||
#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
|
||||
#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0
|
||||
#define DT_GPIO_SAM_PORTA_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_SAM_PORTA_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID
|
||||
#define DT_GPIO_SAM_PORTB_LABEL DT_ATMEL_SAM_GPIO_400E1000_LABEL
|
||||
#define DT_GPIO_SAM_PORTB_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS
|
||||
#define DT_GPIO_SAM_PORTB_IRQ DT_ATMEL_SAM_GPIO_400E1000_IRQ_0
|
||||
#define DT_GPIO_SAM_PORTB_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_SAM_PORTB_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID
|
||||
#define DT_GPIO_SAM_PORTC_LABEL DT_ATMEL_SAM_GPIO_400E1200_LABEL
|
||||
#define DT_GPIO_SAM_PORTC_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS
|
||||
#define DT_GPIO_SAM_PORTC_IRQ DT_ATMEL_SAM_GPIO_400E1200_IRQ_0
|
||||
#define DT_GPIO_SAM_PORTC_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_SAM_PORTC_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID
|
||||
#define DT_GPIO_SAM_PORTD_LABEL DT_ATMEL_SAM_GPIO_400E1400_LABEL
|
||||
#define DT_GPIO_SAM_PORTD_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1400_BASE_ADDRESS
|
||||
#define DT_GPIO_SAM_PORTD_IRQ DT_ATMEL_SAM_GPIO_400E1400_IRQ_0
|
||||
#define DT_GPIO_SAM_PORTD_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1400_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_SAM_PORTD_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1400_PERIPHERAL_ID
|
||||
#define DT_GPIO_SAM_PORTE_LABEL DT_ATMEL_SAM_GPIO_400E1600_LABEL
|
||||
#define DT_GPIO_SAM_PORTE_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1600_BASE_ADDRESS
|
||||
#define DT_GPIO_SAM_PORTE_IRQ DT_ATMEL_SAM_GPIO_400E1600_IRQ_0
|
||||
#define DT_GPIO_SAM_PORTE_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1600_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_SAM_PORTE_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1600_PERIPHERAL_ID
|
||||
|
||||
#define DT_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_400A8000_BASE_ADDRESS
|
||||
#define DT_I2C_0_NAME DT_ATMEL_SAM_I2C_TWI_400A8000_LABEL
|
||||
#define DT_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWI_400A8000_CLOCK_FREQUENCY
|
||||
#define DT_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWI_400A8000_IRQ_0
|
||||
#define DT_I2C_0_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_400A8000_IRQ_0_PRIORITY
|
||||
#define DT_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_400A8000_PERIPHERAL_ID
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_400AC000_BASE_ADDRESS
|
||||
#define DT_I2C_1_NAME DT_ATMEL_SAM_I2C_TWI_400AC000_LABEL
|
||||
#define DT_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWI_400AC000_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWI_400AC000_IRQ_0
|
||||
#define DT_I2C_1_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_400AC000_IRQ_0_PRIORITY
|
||||
#define DT_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_400AC000_PERIPHERAL_ID
|
||||
|
||||
#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40088000_BASE_ADDRESS
|
||||
#define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40088000_LABEL
|
||||
#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40088000_IRQ_0
|
||||
#define DT_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40088000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40088000_PERIPHERAL_ID
|
||||
|
||||
#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0600_LABEL
|
||||
#define DT_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0600_CURRENT_SPEED
|
||||
#define DT_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0600_IRQ_0
|
||||
#define DT_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0600_IRQ_0_PRIORITY
|
||||
#define DT_UART_SAM_PORT_1_NAME DT_ATMEL_SAM_UART_40060600_LABEL
|
||||
#define DT_UART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_UART_40060600_CURRENT_SPEED
|
||||
#define DT_UART_SAM_PORT_1_IRQ DT_ATMEL_SAM_UART_40060600_IRQ_0
|
||||
#define DT_UART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_UART_40060600_IRQ_0_PRIORITY
|
||||
#define DT_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_400A0000_LABEL
|
||||
#define DT_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_400A0000_CURRENT_SPEED
|
||||
#define DT_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_400A4000_LABEL
|
||||
#define DT_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_400A4000_CURRENT_SPEED
|
||||
|
||||
#define DT_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0
|
||||
#define DT_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0_PRIORITY
|
||||
#define DT_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1850_LABEL
|
||||
#define DT_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1850_BASE_ADDRESS
|
||||
/* End of SoC Level DTS fixup file */
|
9
soc/arm/atmel_sam/sam4e/linker.ld
Normal file
9
soc/arm/atmel_sam/sam4e/linker.ld
Normal file
|
@ -0,0 +1,9 @@
|
|||
/* linker.ld - Linker command/script file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
|
224
soc/arm/atmel_sam/sam4e/soc.c
Normal file
224
soc/arm/atmel_sam/sam4e/soc.c
Normal file
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Gerson Fernando Budke
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAM4E MCU series initialization code
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM4E series processor.
|
||||
*/
|
||||
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include <soc.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/arm/aarch32/cortex_m/cmsis.h>
|
||||
|
||||
/**
|
||||
* @brief Setup various clock on SoC at boot time.
|
||||
*
|
||||
* Setup the SoC clocks according to section 28.12 in datasheet.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
u32_t reg_val;
|
||||
|
||||
#ifdef CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK
|
||||
/* Switch slow clock to the external 32 KHz crystal oscillator. */
|
||||
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
|
||||
|
||||
/* Wait for oscillator to be stabilized. */
|
||||
while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
|
||||
;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK */
|
||||
|
||||
#ifdef CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK
|
||||
/*
|
||||
* Setup main external crystal oscillator.
|
||||
*/
|
||||
|
||||
/* Start the external crystal oscillator. */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
|
||||
/* Fast RC oscillator frequency is at 4 MHz. */
|
||||
| CKGR_MOR_MOSCRCF_4_MHz
|
||||
/*
|
||||
* We select maximum setup time. While start up time
|
||||
* could be shortened this optimization is not deemed
|
||||
* critical right now.
|
||||
*/
|
||||
| CKGR_MOR_MOSCXTST(0xFFu)
|
||||
/* RC oscillator must stay on. */
|
||||
| CKGR_MOR_MOSCRCEN
|
||||
| CKGR_MOR_MOSCXTEN;
|
||||
|
||||
/* Wait for oscillator to be stabilized. */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Select the external crystal oscillator as the main clock source. */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
|
||||
| CKGR_MOR_MOSCRCF_4_MHz
|
||||
| CKGR_MOR_MOSCRCEN
|
||||
| CKGR_MOR_MOSCXTEN
|
||||
| CKGR_MOR_MOSCXTST(0xFFu)
|
||||
| CKGR_MOR_MOSCSEL;
|
||||
|
||||
/* Wait for external oscillator to be selected. */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Turn off RC oscillator, not used any longer, to save power */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
|
||||
| CKGR_MOR_MOSCSEL
|
||||
| CKGR_MOR_MOSCXTST(0xFFu)
|
||||
| CKGR_MOR_MOSCXTEN;
|
||||
|
||||
/* Wait for the RC oscillator to be turned off. */
|
||||
while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
|
||||
;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_ATMEL_SAM4E_WAIT_MODE
|
||||
/*
|
||||
* Instruct CPU to enter Wait mode instead of Sleep mode to
|
||||
* keep Processor Clock (HCLK) and thus be able to debug
|
||||
* CPU using JTAG.
|
||||
*/
|
||||
PMC->PMC_FSMR |= PMC_FSMR_LPM;
|
||||
#endif
|
||||
#else
|
||||
/* Setup main fast RC oscillator. */
|
||||
|
||||
/*
|
||||
* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
|
||||
* register, should normally be the case.
|
||||
*/
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Set main fast RC oscillator to 12 MHz. */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
|
||||
| CKGR_MOR_MOSCRCF_12_MHz
|
||||
| CKGR_MOR_MOSCRCEN;
|
||||
|
||||
/* Wait for RC oscillator to stabilize. */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
|
||||
;
|
||||
}
|
||||
#endif /* CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK */
|
||||
|
||||
/*
|
||||
* Setup PLLA
|
||||
*/
|
||||
|
||||
/* Switch MCK (Master Clock) to the main clock first. */
|
||||
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
|
||||
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
|
||||
|
||||
/* Wait for clock selection to complete. */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Setup PLLA. */
|
||||
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
|
||||
| CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM4E_PLLA_MULA)
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3Fu)
|
||||
| CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM4E_PLLA_DIVA);
|
||||
|
||||
/*
|
||||
* NOTE: Both MULA and DIVA must be set to a value greater than 0 or
|
||||
* otherwise PLL will be disabled. In this case we would get stuck in
|
||||
* the following loop.
|
||||
*/
|
||||
|
||||
/* Wait for PLL lock. */
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Final setup of the Master Clock
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: PMC_MCKR must not be programmed in a single write operation.
|
||||
* If CSS or PRES are modified we must wait for MCKRDY bit to be
|
||||
* set again.
|
||||
*/
|
||||
|
||||
/* Setup prescaler - PLLA Clock / Processor Clock (HCLK). */
|
||||
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
|
||||
PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
|
||||
|
||||
/* Wait for Master Clock setup to complete */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Finally select PLL as Master Clock source. */
|
||||
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
|
||||
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
|
||||
|
||||
/* Wait for Master Clock setup to complete. */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run from the very beginning.
|
||||
* So the init priority has to be 0 (zero).
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int atmel_sam4e_init(struct device *arg)
|
||||
{
|
||||
u32_t key;
|
||||
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
/*
|
||||
* Set FWS (Flash Wait State) value before increasing Master Clock
|
||||
* (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
|
||||
* This is set to the highest number of read cycles because it won't
|
||||
* hurt lower clock frequencies. However, a high frequency with too
|
||||
* few read cycles could cause flash read problems. FWS 5 (6 cycles)
|
||||
* is the safe setting for all of this SoCs usable frequencies.
|
||||
*/
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(5);
|
||||
|
||||
/* Setup system clocks. */
|
||||
clock_init();
|
||||
|
||||
/*
|
||||
* Install default handler that simply resets the CPU
|
||||
* if configured in the kernel, NOP otherwise.
|
||||
*/
|
||||
NMI_INIT();
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(atmel_sam4e_init, PRE_KERNEL_1, 0);
|
49
soc/arm/atmel_sam/sam4e/soc.h
Normal file
49
soc/arm/atmel_sam/sam4e/soc.h
Normal file
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Gerson Fernando Budke
|
||||
* Copyright (c) 2018 Vincent van der Locht
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Atmel SAM4E family processors.
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM4E_SOC_H_
|
||||
#define _ATMEL_SAM4E_SOC_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_PART_NUMBER_SAM4E16E)
|
||||
#include <sam4e16e.h>
|
||||
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E16C)
|
||||
#include <sam4e16c.h>
|
||||
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8E)
|
||||
#include <sam4e8e.h>
|
||||
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8C)
|
||||
#include <sam4e8c.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "soc_pinmap.h"
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
|
||||
|
||||
#endif /* _ATMEL_SAM4E_SOC_H_ */
|
63
soc/arm/atmel_sam/sam4e/soc_pinmap.h
Normal file
63
soc/arm/atmel_sam/sam4e/soc_pinmap.h
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Gerson Fernando Budke
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM4E MCU pin definitions.
|
||||
*
|
||||
* This file contains pin configuration data required by different MCU
|
||||
* modules to correctly configure GPIO controller.
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM4E_SOC_PINMAP_H_
|
||||
#define _ATMEL_SAM4E_SOC_PINMAP_H_
|
||||
|
||||
#include <soc.h>
|
||||
|
||||
/* Universal Asynchronous Receiver Transmitter (UART) */
|
||||
|
||||
#define PIN_UART0_RXD {PIO_PA9A_URXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
#define PIN_UART0_TXD {PIO_PA10A_UTXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
|
||||
#define PINS_UART0 {PIN_UART0_RXD, PIN_UART0_TXD}
|
||||
|
||||
#define PIN_UART1_RXD {PIO_PA5C_URXD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
#define PIN_UART1_TXD {PIO_PA6C_UTXD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
|
||||
#define PINS_UART1 {PIN_UART1_RXD, PIN_UART1_TXD}
|
||||
|
||||
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||||
|
||||
#define PIN_USART0_RXD {PIO_PB0C_RXD0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
#define PIN_USART0_TXD {PIO_PB1C_TXD0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
#define PIN_USART0_CTS {PIO_PB2C_CTS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
#define PIN_USART0_RTS {PIO_PB3C_RTS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
#define PIN_USART0_SCK {PIO_PB13C_SCK0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C}
|
||||
|
||||
#define PINS_USART0 {PIN_USART0_RXD, PIN_USART0_TXD, PIN_USART0_CTS, \
|
||||
PIN_USART0_RTS, PIN_USART0_SCK}
|
||||
|
||||
#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
#define PIN_USART1_TXD {PIO_PA22A_TXD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_D}
|
||||
#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
|
||||
#define PINS_USART1 {PIN_USART1_RXD, PIN_USART1_TXD, PIN_USART1_CTS, \
|
||||
PIN_USART1_RTS, PIN_USART1_SCK}
|
||||
|
||||
/* Two-wire Interface (TWI) */
|
||||
|
||||
#define PIN_TWI0_TWCK {PIO_PA4A_TWCK0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
#define PIN_TWI0_TWD {PIO_PA3A_TWD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
|
||||
|
||||
#define PINS_TWI0 {PIN_TWI0_TWCK, PIN_TWI0_TWD}
|
||||
|
||||
#define PIN_TWI1_TWCK {PIO_PB5A_TWCK1, PIOB, ID_PIOB, SOC_GPIO_FUNC_A}
|
||||
#define PIN_TWI1_TWD {PIO_PB4A_TWD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_A}
|
||||
|
||||
#define PINS_TWI1 {PIN_TWI1_TWCK, PIN_TWI1_TWD}
|
||||
|
||||
#endif /* _ATMEL_SAM4E_SOC_PINMAP_H_ */
|
Loading…
Add table
Add a link
Reference in a new issue