From 497f2ce835cd61a674581ddb3bd3d62887eb3ce6 Mon Sep 17 00:00:00 2001
From: Sadik Ozer <sadik.ozer@analog.com>
Date: Fri, 5 Jan 2024 11:40:58 +0300
Subject: [PATCH] dts: adi: Enable low-power pin modes

low-power pins can be used while device power management enabled.
Usage

...
&uart0a_rx_p0_0 {
  pinmux = <MAX32_PINMUX(0, 0, AF1)>;
  low-power-enable;
  /* Add low power mode flags, like: */
  output-high;
  bias-disable;
  ...
};
...

Default gpio sleep states are defined, user shall update sleep_pins
configuration as per of their needs

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
---
 dts/arm/adi/max32/max32655-pinctrl.dtsi     | 487 ++++++++++
 dts/arm/adi/max32/max32662-pinctrl.dtsi     | 287 ++++++
 dts/arm/adi/max32/max32666-pinctrl.dtsi     | 797 ++++++++++++++++
 dts/arm/adi/max32/max32670-pinctrl.dtsi     | 447 +++++++++
 dts/arm/adi/max32/max32672-pinctrl.dtsi     | 642 +++++++++++++
 dts/arm/adi/max32/max32675-pinctrl.dtsi     | 257 ++++++
 dts/arm/adi/max32/max32680-pinctrl.dtsi     | 357 ++++++++
 dts/arm/adi/max32/max32690-pinctrl.dtsi     | 952 ++++++++++++++++++++
 dts/bindings/pinctrl/adi,max32-pinctrl.yaml |   1 +
 9 files changed, 4227 insertions(+)

diff --git a/dts/arm/adi/max32/max32655-pinctrl.dtsi b/dts/arm/adi/max32/max32655-pinctrl.dtsi
index c336e402afc..04f52077308 100644
--- a/dts/arm/adi/max32/max32655-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32655-pinctrl.dtsi
@@ -405,3 +405,490 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ uart0a_rx_p0_0_sleep: uart0a_rx_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p0_1_sleep: uart0a_tx_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0a_ioa_p0_2_sleep: tmr0a_ioa_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_cts_p0_2_sleep: uart0b_cts_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk_p0_3_sleep: ext_clk_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rts_p0_3_sleep: uart0b_rts_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss0_p0_4_sleep: spi0_ss0_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_ioan_p0_4_sleep: tmr0b_ioan_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_mosi_p0_5_sleep: spi0_mosi_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_iobn_p0_5_sleep: tmr0b_iobn_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_miso_p0_6_sleep: spi0_miso_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_6_sleep: owm_io_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sck_p0_7_sleep: spi0_sck_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_7_sleep: owm_pe_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sdio2_p0_8_sleep: spi0_sdio2_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_ioa_p0_8_sleep: tmr0b_ioa_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sdio3_p0_9_sleep: spi0_sdio3_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_iob_p0_9_sleep: tmr0b_iob_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0_scl_p0_10_sleep: i2c0_scl_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss2_p0_10_sleep: spi0_ss2_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0_sda_p0_11_sleep: i2c0_sda_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss1_p0_11_sleep: spi0_ss1_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rx_p0_12_sleep: uart1a_rx_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_ioan_p0_12_sleep: tmr1b_ioan_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_tx_p0_13_sleep: uart1a_tx_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_iobn_p0_13_sleep: tmr1b_iobn_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1a_ioa_p0_14_sleep: tmr1a_ioa_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_cts_p0_14_sleep: uart1b_cts_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1a_iob_p0_15_sleep: tmr1a_iob_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rts_p0_15_sleep: uart1b_rts_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1_scl_p0_16_sleep: i2c1_scl_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2_p0_16_sleep: pt2_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1_sda_p0_17_sleep: i2c1_sda_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt3_p0_17_sleep: pt3_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt0_p0_18_sleep: pt0_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_18_sleep: owm_io_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt1_p0_19_sleep: pt1_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_19_sleep: owm_pe_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss0_p0_20_sleep: spi1_ss0_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_ioa_p0_20_sleep: tmr1b_ioa_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_mosi_p0_21_sleep: spi1_mosi_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_iob_p0_21_sleep: tmr1b_iob_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_miso_p0_22_sleep: spi1_miso_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_ioan_p0_22_sleep: tmr1b_ioan_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sck_p0_23_sleep: spi1_sck_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_iobn_p0_23_sleep: tmr1b_iobn_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sdio2_p0_24_sleep: spi1_sdio2_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2b_ioa_p0_24_sleep: tmr2b_ioa_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sdio3_p0_25_sleep: spi1_sdio3_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2b_iob_p0_25_sleep: tmr2b_iob_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2a_ioa_p0_26_sleep: tmr2a_ioa_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss1_p0_26_sleep: spi1_ss1_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2a_iob_p0_27_sleep: tmr2a_iob_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss2_p0_27_sleep: spi1_ss2_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdio_p0_28_sleep: swdio_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swclk_p0_29_sleep: swclk_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2_scl_p0_30_sleep: i2c2_scl_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_cts_p0_30_sleep: uart2b_cts_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2_sda_p0_31_sleep: i2c2_sda_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rts_p0_31_sleep: uart2b_rts_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rx_p1_0_sleep: uart2a_rx_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tck_p1_0_sleep: rv_tck_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_tx_p1_1_sleep: uart2a_tx_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tms_p1_1_sleep: rv_tms_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s_sck_p1_2_sleep: i2s_sck_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tdi_p1_2_sleep: rv_tdi_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s_ws_p1_3_sleep: i2s_ws_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tdo_p1_3_sleep: rv_tdo_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s_sdi_p1_4_sleep: i2s_sdi_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3b_ioa_p1_4_sleep: tmr3b_ioa_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s_sdo_p1_5_sleep: i2s_sdo_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3b_iob_p1_5_sleep: tmr3b_iob_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3a_ioa_p1_6_sleep: tmr3a_ioa_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl2_p1_6_sleep: ble_ant_ctrl2_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3a_iob_p1_7_sleep: tmr3a_iob_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl3_p1_7_sleep: ble_ant_ctrl3_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctr_p1_8_sleep: ble_ant_ctr_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rxev0l0_p1_8_sleep: rxev0l0_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctr_p1_9_sleep: ble_ant_ctr_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ txev0l1_p1_9_sleep: txev0l1_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain0_p2_0_sleep: ain0_p2_0_sleep {
+		pinmux = <MAX32_PINMUX(2, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain1_p2_1_sleep: ain1_p2_1_sleep {
+		pinmux = <MAX32_PINMUX(2, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain2_p2_2_sleep: ain2_p2_2_sleep {
+		pinmux = <MAX32_PINMUX(2, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain3_p2_3_sleep: ain3_p2_3_sleep {
+		pinmux = <MAX32_PINMUX(2, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain4_p2_4_sleep: ain4_p2_4_sleep {
+		pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_ioa_p2_4_sleep: lptmr0b_ioa_p2_4_sleep {
+		pinmux = <MAX32_PINMUX(2, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain5_p2_5_sleep: ain5_p2_5_sleep {
+		pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1b_ioa_p2_5_sleep: lptmr1b_ioa_p2_5_sleep {
+		pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0_clk_p2_6_sleep: lptmr0_clk_p2_6_sleep {
+		pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuartb_rx_p2_6_sleep: lpuartb_rx_p2_6_sleep {
+		pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1_clk_p2_7_sleep: lptmr1_clk_p2_7_sleep {
+		pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuartb_tx_p2_7_sleep: lpuartb_tx_p2_7_sleep {
+		pinmux = <MAX32_PINMUX(2, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pdown_p3_0_sleep: pdown_p3_0_sleep {
+		pinmux = <MAX32_PINMUX(3, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ wakeup_p3_0_sleep: wakeup_p3_0_sleep {
+		pinmux = <MAX32_PINMUX(3, 0, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sqwout_p3_1_sleep: sqwout_p3_1_sleep {
+		pinmux = <MAX32_PINMUX(3, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ wakeup_p3_1_sleep: wakeup_p3_1_sleep {
+		pinmux = <MAX32_PINMUX(3, 1, AF2)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32662-pinctrl.dtsi b/dts/arm/adi/max32/max32662-pinctrl.dtsi
index 7c8d7a2fb13..2ec93d74e91 100644
--- a/dts/arm/adi/max32/max32662-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32662-pinctrl.dtsi
@@ -342,3 +342,290 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ swdio_p0_0_sleep: swdio_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt0b_p0_0_sleep: pt0b_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_0_sleep: tmr0c_oa_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1d_oa_p0_0_sleep: tmr1d_oa_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_e_p0_0_sleep: adc_trig_e_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdclk_p0_1_sleep: swdclk_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt1b_p0_1_sleep: pt1b_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_1_sleep: tmr0c_ia_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1d_ia_p0_1_sleep: tmr1d_ia_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_cito_p0_2_sleep: spi0a_cito_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_tx_p0_2_sleep: uart1b_tx_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_2_sleep: tmr0c_ia_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt0d_p0_2_sleep: pt0d_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0e_sdo_p0_2_sleep: i2s0e_sdo_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_copi_p0_3_sleep: spi0a_copi_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rx_p0_3_sleep: uart1b_rx_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_3_sleep: tmr0c_oa_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt1d_p0_3_sleep: pt1d_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0e_sdi_p0_3_sleep: i2s0e_sdi_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_sck_p0_4_sleep: spi0a_sck_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_cts_p0_4_sleep: uart1b_cts_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_4_sleep: tmr1c_ia_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2d_p0_4_sleep: pt2d_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0e_bclk_p0_4_sleep: i2s0e_bclk_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_ts0_p0_5_sleep: spi0a_ts0_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rts_p0_5_sleep: uart1b_rts_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_5_sleep: tmr1c_oa_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt3d_p0_5_sleep: pt3d_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0e_lrclk_p0_5_sleep: i2s0e_lrclk_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_scl_p0_6_sleep: i2c1a_scl_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can0b_rx_p0_6_sleep: can0b_rx_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_6_sleep: tmr2c_ia_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hf_ext_clk_p0_6_sleep: hf_ext_clk_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2e_p0_6_sleep: pt2e_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_sda_p0_9_sleep: i2c1a_sda_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can0b_tx_p0_9_sleep: can0b_tx_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_9_sleep: tmr2c_oa_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_d_p0_9_sleep: adc_trig_d_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt3e_p0_9_sleep: pt3e_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p0_10_sleep: uart0a_tx_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_ts0_p0_10_sleep: spi1b_ts0_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain3_p0_10_sleep: ain3_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rx_p0_11_sleep: uart0a_rx_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_sck_p0_11_sleep: spi1b_sck_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cal32k_p0_11_sleep: cal32k_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain2_p0_11_sleep: ain2_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lp_ext_clk_p0_11_sleep: lp_ext_clk_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_scl_p0_12_sleep: i2c0a_scl_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_coti_p0_12_sleep: spi1b_coti_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0c_ia_p0_12_sleep: lptmr0c_ia_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain1_p0_12_sleep: ain1_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0e_oan_p0_12_sleep: lptmr0e_oan_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF5)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_sda_p0_13_sleep: i2c0a_sda_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_cito_p0_13_sleep: spi1b_cito_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0c_oa_p0_13_sleep: lptmr0c_oa_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain0_p0_13_sleep: ain0_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32666-pinctrl.dtsi b/dts/arm/adi/max32/max32666-pinctrl.dtsi
index a44553f74a0..46b2215a320 100644
--- a/dts/arm/adi/max32/max32666-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32666-pinctrl.dtsi
@@ -644,3 +644,800 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ spixf_ss0_p0_0_sleep: spixf_ss0_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_cts_p0_0_sleep: uart2_cts_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0_p0_0_sleep: tmr0_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_mosi_p0_1_sleep: spixf_mosi_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_tx_p0_1_sleep: uart2_tx_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1_p0_1_sleep: tmr1_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_miso_p0_2_sleep: spixf_miso_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_rx_p0_2_sleep: uart2_rx_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2_p0_2_sleep: tmr2_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sck_p0_3_sleep: spixf_sck_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_rts_p0_3_sleep: uart2_rts_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3_p0_3_sleep: tmr3_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sdio2_p0_4_sleep: spixf_sdio2_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_4_sleep: owm_io_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr4_p0_4_sleep: tmr4_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sdio3_p0_5_sleep: spixf_sdio3_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/owm_pe_p0_5_sleep: owm_pe_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr5_p0_5_sleep: tmr5_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0_scl_p0_6_sleep: i2c0_scl_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdio2_p0_6_sleep: swdio2_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0_p0_6_sleep: tmr0_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0_sda_p0_7_sleep: i2c0_sda_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swclk2_p0_7_sleep: swclck2_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1_p0_7_sleep: tmr1_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_ss0_p0_8_sleep: spixr_ss0_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss0_p0_8_sleep: spi0_ss0_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_cts_p0_8_sleep: uart0_cts_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2_p0_8_sleep: tmr2_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_mosi_p0_9_sleep: spixr_mosi_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_mosi_p0_9_sleep: spi0_mosi_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_tx_p0_9_sleep: uart0_tx_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3_p0_9_sleep: tmr3_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_miso_p0_10_sleep: spixr_miso_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_miso_p0_10_sleep: spi0_miso_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_rx_p0_10_sleep: uart0_rx_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr4_p0_10_sleep: tmr4_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sck_p0_11_sleep: spixr_sck_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sck_p0_11_sleep: spi0_sck_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_rts_p0_11_sleep: uart0_rts_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr5_p0_11_sleep: tmr5_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sdio2_p0_12_sleep: spixr_sdio2_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sdio2_p0_12_sleep: spi0_sdio2_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_12_sleep: owm_io_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0_p0_12_sleep: tmr0_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sdio3_p0_13_sleep: spixr_sdio3_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sdio3_p0_13_sleep: spi0_sdio3_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_13_sleep: owm_pe_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1_p0_13_sleep: tmr1_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1_scl_p0_14_sleep: i2c1_scl_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss1_p0_14_sleep: spi0_ss1_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2_p0_14_sleep: tmr2_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1_sda_p0_15_sleep: i2c1_sda_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss2_p0_15_sleep: spi0_ss2_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3_p0_15_sleep: tmr3_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain0n_p0_16_sleep: ain0n_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss0_p0_16_sleep: spi1_ss0_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_16_sleep: owm_io_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr4_p0_16_sleep: tmr4_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain0p_p0_17_sleep: ain0p_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_mosi_p0_17_sleep: spi1_mosi_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_17_sleep: owm_pe_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr5_p0_17_sleep: tmr5_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain1n_p0_18_sleep: ain1n_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_miso_p0_18_sleep: spi1_miso_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0_p0_18_sleep: tmr0_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain1p_p0_19_sleep: ain1p_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sck_p0_19_sleep: spi1_sck_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1_p0_19_sleep: tmr1_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain2n_p0_20_sleep: ain2n_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sdio2_p0_20_sleep: spi1_sdio2_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_rx_p0_20_sleep: uart1_rx_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2_p0_20_sleep: tmr2_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain2p_p0_21_sleep: ain2p_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sdio3_p0_21_sleep: spi1_sdio3_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_tx_p0_21_sleep: uart1_tx_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3_p0_21_sleep: tmr3_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain3n_p0_22_sleep: ain3n_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss1_p0_22_sleep: spi1_ss1_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_cts_p0_22_sleep: uart1_cts_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr4_p0_22_sleep: tmr4_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain3p_p0_23_sleep: ain3p_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss2_p0_23_sleep: spi1_ss2_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_rts_p0_23_sleep: uart1_rts_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr5_p0_23_sleep: tmr5_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pcm_lrclk_p0_24_sleep: pcm_lrclk_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_ss0_p0_24_sleep: spi2_ss0_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_24_sleep: owm_io_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0_p0_24_sleep: tmr0_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pcm_dout_p0_25_sleep: pcm_dout_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_mosi_p0_25_sleep: spi2_mosi_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_25_sleep: owm_pe_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1_p0_25_sleep: tmr1_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pcm_din_p0_26_sleep: pcm_din_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_miso_p0_26_sleep: spi2_miso_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2_p0_26_sleep: tmr2_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pcm_bclk_p0_27_sleep: pcm_bclk_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_sck_p0_27_sleep: spi2_sck_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3_p0_27_sleep: tmr3_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pdm_data2_p0_28_sleep: pdm_data2_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_sdio2_p0_28_sleep: spi2_sdio2_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_rx_p0_28_sleep: uart2_rx_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr4_p0_28_sleep: tmr4_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pdm_data3_p0_29_sleep: pdm_data3_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_sdio3_p0_29_sleep: spi2_sdio3_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_tx_p0_29_sleep: uart2_tx_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr5_p0_29_sleep: tmr5_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pdm_rx_clk_p0_30_sleep: pdm_rx_clk_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_ss1_p0_30_sleep: spi2_ss1_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_cts_p0_30_sleep: uart2_cts_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0_p0_30_sleep: tmr0_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pdm_mclk_p0_31_sleep: pdm_mclk_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2_ss2_p0_31_sleep: spi2_ss2_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2_rts_p0_31_sleep: uart2_rts_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1_p0_31_sleep: tmr1_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_dat3_p1_0_sleep: sdhc_dat3_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdma_tms_p1_0_sleep: sdma_tms_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt0_p1_0_sleep: pt0_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_cmd_p1_1_sleep: sdhc_cmd_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdma_tdo_p1_1_sleep: sdma_tdo_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt1_p1_1_sleep: pt1_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_dat0_p1_2_sleep: sdhc_dat0_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdma_tdi_p1_2_sleep: sdma_tdi_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2_p1_2_sleep: pt2_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_clk_p1_3_sleep: sdhc_clk_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdma_tck_p1_3_sleep: sdma_tck_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt3_p1_3_sleep: pt3_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_dat1_p1_4_sleep: sdhc_dat1_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_rx_p1_4_sleep: uart0_rx_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt5_p1_4_sleep: pt5_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_dat2_p1_5_sleep: sdhc_dat2_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_tx_p1_5_sleep: uart0_tx_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt5_p1_5_sleep: pt5_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_wp_p1_6_sleep: sdhc_wp_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_cts_p1_6_sleep: uart0_cts_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt6_p1_6_sleep: pt6_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ sdhc_cdn_p1_7_sleep: sdhc_cdn_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0_rts_p1_7_sleep: uart0_rts_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt7_p1_7_sleep: pt7_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss0_p1_8_sleep: spi0_ss0_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt8_p1_8_sleep: pt8_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_mosi_p1_9_sleep: spi0_mosi_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt9_p1_9_sleep: pt9_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_miso_p1_10_sleep: spi0_miso_p1_10_sleep {
+		pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt10_p1_10_sleep: pt10_p1_10_sleep {
+		pinmux = <MAX32_PINMUX(1, 10, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sck_p1_11_sleep: spi0_sck_p1_11_sleep {
+		pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt11_p1_11_sleep: pt11_p1_11_sleep {
+		pinmux = <MAX32_PINMUX(1, 11, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sdio2_p1_12_sleep: spi0_sdio2_p1_12_sleep {
+		pinmux = <MAX32_PINMUX(1, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_rx_p1_12_sleep: uart1_rx_p1_12_sleep {
+		pinmux = <MAX32_PINMUX(1, 12, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt12_p1_12_sleep: pt12_p1_12_sleep {
+		pinmux = <MAX32_PINMUX(1, 12, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sdio3_p1_13_sleep: spi0_sdio3_p1_13_sleep {
+		pinmux = <MAX32_PINMUX(1, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_tx_p1_13_sleep: uart1_tx_p1_13_sleep {
+		pinmux = <MAX32_PINMUX(1, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt13_p1_13_sleep: pt13_p1_13_sleep {
+		pinmux = <MAX32_PINMUX(1, 13, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2_scl_p1_14_sleep: i2c2_scl_p1_14_sleep {
+		pinmux = <MAX32_PINMUX(1, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_cts_p1_14_sleep: uart1_cts_p1_14_sleep {
+		pinmux = <MAX32_PINMUX(1, 14, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt14_p1_14_sleep: pt14_p1_14_sleep {
+		pinmux = <MAX32_PINMUX(1, 14, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2_sda_p1_15_sleep: i2c2_sda_p1_15_sleep {
+		pinmux = <MAX32_PINMUX(1, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1_rts_p1_15_sleep: uart1_rts_p1_15_sleep {
+		pinmux = <MAX32_PINMUX(1, 15, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt15_p1_15_sleep: pt15_p1_15_sleep {
+		pinmux = <MAX32_PINMUX(1, 15, AF4)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32670-pinctrl.dtsi b/dts/arm/adi/max32/max32670-pinctrl.dtsi
index 29cf03f2aad..b1fd9154ee5 100644
--- a/dts/arm/adi/max32/max32670-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32670-pinctrl.dtsi
@@ -365,3 +365,450 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ swdio_p0_0_sleep: swdio_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_0_sleep: tmr0c_ia_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdclk_p0_1_sleep: swdclk_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_o_p0_1_sleep: tmr0c_o_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_miso_p0_2_sleep: spi0_miso_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rx_p0_2_sleep: uart1b_rx_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_2_sleep: tmr1c_ia_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_mosi_p0_3_sleep: spi0_mosi_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_tx_p0_3_sleep: uart1b_tx_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_3_sleep: tmr1c_oa_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_sck_p0_4_sleep: spi0_sck_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_cts_p0_4_sleep: uart1b_cts_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_4_sleep: tmr2c_ia_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0_ss0_p0_5_sleep: spi0_ss0_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rts_p0_5_sleep: uart1b_rts_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_5_sleep: tmr2c_oa_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ div_clk_outa_p0_5_sleep: div_clk_outa_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0_scl_p0_6_sleep: i2c0_scl_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_ia_p0_6_sleep: lptmr0b_ia_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_6_sleep: tmr3c_ia_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0_sda_p0_7_sleep: i2c0_sda_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_oa_p0_7_sleep: lptmr0b_oa_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_7_sleep: tmr3c_oa_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rx_p0_8_sleep: uart0a_rx_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0_sdo_p0_8_sleep: i2s0_sdo_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_8_sleep: tmr0c_ia_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p0_9_sleep: uart0a_tx_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0_lrclk_p0_9_sleep: i2s0_lrclk_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_9_sleep: tmr0c_oa_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_cts_p0_10_sleep: uart0a_cts_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0_bclk_p0_10_sleep: i2s0_bclk_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_10_sleep: tmr1c_ia_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ div_clk_outb_p0_10_sleep: div_clk_outb_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rts_p0_11_sleep: uart0a_rts_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0_sdi_p0_11_sleep: i2s0_sdi_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_11_sleep: tmr1c_oa_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1_scl_p0_12_sleep: i2c1_scl_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk2_p0_12_sleep: ext_clk2_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_12_sleep: tmr2c_ia_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk1_p0_12_sleep: ext_clk1_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1_sda_p0_13_sleep: i2c1_sda_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cal32k_p0_13_sleep: cal32k_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_13_sleep: tmr2c_oa_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss0_p0_13_sleep: spi1_ss0_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_miso_p0_14_sleep: spi1_miso_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rx_p0_14_sleep: uart2b_rx_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_14_sleep: tmr3c_ia_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_mosi_p0_15_sleep: spi1_mosi_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_tx_p0_15_sleep: uart2b_tx_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_15_sleep: tmr3c_oa_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_sck_p0_16_sleep: spi1_sck_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_cts_p0_16_sleep: uart2b_cts_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_16_sleep: tmr0c_ia_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss0_p0_17_sleep: spi1_ss0_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rts_p0_17_sleep: uart2b_rts_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_17_sleep: tmr0c_oa_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2_scl_p0_18_sleep: i2c2_scl_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_18_sleep: tmr1c_ia_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2_sda_p0_19_sleep: i2c2_sda_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_19_sleep: tmr1c_oa_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cm4_rx_p0_20_sleep: cm4_rx_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_20_sleep: tmr2c_ia_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdclkb_p0_20_sleep: swdclkb_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cm4_tx_p0_21_sleep: cm4_tx_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_21_sleep: tmr2c_oa_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1a_ia_p0_22_sleep: lptmr1a_ia_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_22_sleep: tmr3c_ia_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdiob_p0_22_sleep: swdiob_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1a_oa_p0_23_sleep: lptmr1a_oa_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_23_sleep: tmr3c_oa_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0_cts_p0_24_sleep: lpuart0_cts_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rx_p0_24_sleep: uart0b_rx_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_24_sleep: tmr0c_ia_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0_rts_p0_25_sleep: lpuart0_rts_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_tx_p0_25_sleep: uart0b_tx_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_25_sleep: tmr0c_oa_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0_rx_p0_26_sleep: lpuart0_rx_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_cts_p0_26_sleep: uart0b_cts_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_26_sleep: tmr1c_ia_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0_tx_p0_27_sleep: lpuart0_tx_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rts_p0_27_sleep: uart0b_rts_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_27_sleep: tmr1c_oa_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rx_p0_28_sleep: uart1a_rx_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_28_sleep: tmr2c_ia_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_tx_p0_29_sleep: uart1a_tx_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_29_sleep: tmr2c_oa_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_cts_p0_30_sleep: uart1a_cts_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_30_sleep: tmr3c_ia_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF3)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32672-pinctrl.dtsi b/dts/arm/adi/max32/max32672-pinctrl.dtsi
index bbc737cc4d3..c85ee02bc30 100644
--- a/dts/arm/adi/max32/max32672-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32672-pinctrl.dtsi
@@ -520,3 +520,645 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ swdio_p0_0_sleep: swdio_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_0_sleep: tmr0c_ia_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdclk_p0_1_sleep: swdclk_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_1_sleep: tmr0c_oa_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_miso_p0_2_sleep: spi0a_miso_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rx_p0_2_sleep: uart1b_rx_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_2_sleep: tmr1c_ia_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_mosi_p0_3_sleep: spi0a_mosi_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_tx_p0_3_sleep: uart1b_tx_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_3_sleep: tmr1c_oa_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_sck_p0_4_sleep: spi0a_sck_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_cts_p0_4_sleep: uart1b_cts_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_4_sleep: tmr2c_ia_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_ss0_p0_5_sleep: spi0a_ss0_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rts_p0_5_sleep: uart1b_rts_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_5_sleep: tmr2c_oa_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hfx_clk_out_p0_5_sleep: hfx_clk_out_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_scl_p0_6_sleep: i2c0a_scl_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_ia_p0_6_sleep: lptmr0b_ia_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0c_ss1_p0_6_sleep: spi0c_ss1_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qea_p0_6_sleep: qea_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_sda_p0_7_sleep: i2c0a_sda_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_oa_p0_7_sleep: lptmr0b_oa_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0c_ss2_p0_7_sleep: spi0c_ss2_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qeb_p0_7_sleep: qeb_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rx_p0_8_sleep: uart0a_rx_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_sdo_p0_8_sleep: i2s0a_sdo_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_8_sleep: tmr0c_ia_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain0_p0_8_sleep: ain0_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p0_9_sleep: uart0a_tx_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_lrclk_p0_9_sleep: i2s0a_lrclk_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_9_sleep: tmr0c_oa_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_n_p0_9_sleep: ain_c0_n_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_cts_p0_10_sleep: uart0a_cts_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_bcllk_p0_10_sleep: i2s0a_bcllk_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_10_sleep: tmr1c_ia_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_n_p0_10_sleep: ain_c0_n_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rts_p0_11_sleep: uart0a_rts_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_sdi_p0_11_sleep: i2s0a_sdi_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_11_sleep: tmr1c_oa_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_n_p0_11_sleep: ain_c0_n_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_scl_p0_12_sleep: i2c1a_scl_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk2_p0_12_sleep: ext_clk2_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_12_sleep: tmr2c_ia_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_p_p0_12_sleep: ain_c0_p_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_sda_p0_13_sleep: i2c1a_sda_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cal32k_p0_13_sleep: cal32k_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_13_sleep: tmr2c_oa_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_p_p0_13_sleep: ain_c0_p_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_miso_p0_14_sleep: spi1a_miso_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rx_p0_14_sleep: uart2b_rx_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_14_sleep: tmr3c_ia_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_p_p0_14_sleep: ain_c0_p_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_mosi_p0_15_sleep: spi1a_mosi_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_tx_p0_15_sleep: uart2b_tx_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_15_sleep: tmr3c_oa_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain_c0_p_p0_15_sleep: ain_c0_p_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_sck_p0_16_sleep: spi1a_sck_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_cts_p0_16_sleep: uart2b_cts_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_16_sleep: tmr0c_ia_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain8_p0_16_sleep: ain8_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_ss0_p0_17_sleep: spi1a_ss0_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rts_p0_17_sleep: uart2b_rts_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_17_sleep: tmr0c_oa_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain9_p0_17_sleep: ain9_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2a_scl_p0_18_sleep: i2c2a_scl_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_18_sleep: tmr1c_ia_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain10_p0_18_sleep: ain10_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2a_sda_p0_19_sleep: i2c2a_sda_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_19_sleep: tmr1c_oa_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain11_p0_19_sleep: ain11_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cm4_rx_p0_20_sleep: cm4_rx_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ia_p0_20_sleep: tmr2c_ia_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cm4_tx_p0_21_sleep: cm4_tx_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_21_sleep: tmr2c_oa_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1a_ia_p0_22_sleep: lptmr1a_ia_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_b_p0_22_sleep: adc_trig_b_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_22_sleep: tmr0c_ia_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1a_oa_p0_23_sleep: lptmr1a_oa_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0c_ss3_p0_23_sleep: spi0c_ss3_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qei_p0_23_sleep: qei_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0a_cts_p0_24_sleep: lpuart0a_cts_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rx_p0_24_sleep: uart0b_rx_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_sd0_p0_24_sleep: i2s0a_sd0_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qes_p0_24_sleep: qes_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0a_rts_p0_25_sleep: lpuart0a_rts_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_tx_p0_25_sleep: uart0b_tx_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_lrclk_p0_25_sleep: i2s0a_lrclk_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qmatch_p0_25_sleep: qmatch_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0a_rx_p0_26_sleep: lpuart0a_rx_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_cts_p0_26_sleep: uart0b_cts_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0c_bclk_p0_26_sleep: i2s0c_bclk_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qdir_p0_26_sleep: qdir_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0a_tx_p0_27_sleep: lpuart0a_tx_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rts_p0_27_sleep: uart0b_rts_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0c_sdi_p0_27_sleep: i2s0c_sdi_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ qerr_p0_27_sleep: qerr_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rx_p0_28_sleep: uart1a_rx_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk1_p0_28_sleep: ext_clk1_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_28_sleep: tmr3c_ia_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_tx_p0_29_sleep: uart1a_tx_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1_ss0_p0_29_sleep: spi1_ss0_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_29_sleep: tmr3c_oa_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_d_p0_29_sleep: adc_trig_d_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_cts_p0_30_sleep: uart1a_cts_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_30_sleep: tmr3c_ia_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rts_p0_31_sleep: uart1a_rts_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_31_sleep: tmr3c_oa_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p1_0_sleep: tmr1c_ia_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_miso_p1_1_sleep: spi2a_miso_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rx_p1_1_sleep: uart0b_rx_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p1_1_sleep: tmr3c_oa_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_mosi_p1_2_sleep: spi2a_mosi_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_tx_p1_2_sleep: uart0b_tx_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p1_2_sleep: tmr3c_ia_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ div_clk_out_p1_2_sleep: div_clk_out_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_sck_p1_3_sleep: spi2a_sck_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_cts_p1_3_sleep: uart0b_cts_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_ss0_p1_4_sleep: spi2a_ss0_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_rts_p1_4_sleep: uart0b_rts_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p1_4_sleep: tmr0c_oa_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_d_p1_4_sleep: adc_trig_d_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rx_p1_5_sleep: uart2a_rx_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_tx_p1_6_sleep: uart2a_tx_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_cts_p1_7_sleep: uart2a_cts_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rts_p1_8_sleep: uart2a_rts_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p1_9_sleep: tmr1c_oa_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF3)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32675-pinctrl.dtsi b/dts/arm/adi/max32/max32675-pinctrl.dtsi
index 28920ec0b18..a12f52ca876 100644
--- a/dts/arm/adi/max32/max32675-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32675-pinctrl.dtsi
@@ -212,3 +212,260 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ swdio_p0_0_sleep: swdio_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_0_sleep: tmr0c_ia_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdclk_p0_1_sleep: swdclk_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_1_sleep: tmr0c_oa_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_scl_p0_6_sleep: i2c0a_scl_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_ia_p0_6_sleep: lptmr0b_ia_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_6_sleep: tmr3c_ia_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_sda_p0_7_sleep: i2c0a_sda_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_oa_p0_7_sleep: lptmr0b_oa_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_7_sleep: tmr3c_oa_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rx_p0_8_sleep: uart0a_rx_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_sdo_p0_8_sleep: i2s0b_sdo_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_8_sleep: tmr0c_ia_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p0_9_sleep: uart0a_tx_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_lrclk_p0_9_sleep: i2s0b_lrclk_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_9_sleep: tmr0c_oa_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_cts_p0_10_sleep: uart0a_cts_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_bclk_p0_10_sleep: i2s0b_bclk_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_10_sleep: tmr1c_ia_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk_p0_10_sleep: ext_clk_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rts_p0_11_sleep: uart0a_rts_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_sdi_p0_11_sleep: i2s0b_sdi_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_11_sleep: tmr1c_oa_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_13_sleep: tmr2c_oa_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1d_ss0_p0_13_sleep: spi1d_ss0_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_miso_p0_14_sleep: spi1a_miso_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rx_p0_14_sleep: uart2b_rx_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ia_p0_14_sleep: tmr3c_ia_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_mosi_p0_15_sleep: spi1a_mosi_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_tx_p0_15_sleep: uart2b_tx_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_15_sleep: tmr3c_oa_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_sck_p0_16_sleep: spi1a_sck_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_cts_p0_16_sleep: uart2b_cts_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ia_p0_16_sleep: tmr0c_ia_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_ss0_p0_17_sleep: spi1a_ss0_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rts_p0_17_sleep: uart2b_rts_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_oa_p0_17_sleep: tmr0c_oa_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2a_scl_p0_18_sleep: i2c2a_scl_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ia_p0_18_sleep: tmr1c_ia_p0_18_sleep {
+		pinmux = <MAX32_PINMUX(0, 18, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2a_sda_p0_19_sleep: i2c2a_sda_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_oa_p0_19_sleep: tmr1c_oa_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ cm4_tx_p0_21_sleep: cm4_tx_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p0_21_sleep: tmr2c_oa_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_oa_p0_31_sleep: tmr3c_oa_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rx_p1_8_sleep: uart2a_rx_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2b_rts_p1_8_sleep: uart2b_rts_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_tx_p1_9_sleep: uart2a_tx_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_cts_p1_10_sleep: uart2a_cts_p1_10_sleep {
+		pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rts_p1_11_sleep: uart2a_rts_p1_11_sleep {
+		pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_oa_p1_11_sleep: tmr2c_oa_p1_11_sleep {
+		pinmux = <MAX32_PINMUX(1, 11, AF3)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32680-pinctrl.dtsi b/dts/arm/adi/max32/max32680-pinctrl.dtsi
index 525666cb14c..e5649905652 100644
--- a/dts/arm/adi/max32/max32680-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32680-pinctrl.dtsi
@@ -292,3 +292,360 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ uart0a_rx_p0_0_sleep: uart0a_rx_p0_0_sleep {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p0_1_sleep: uart0a_tx_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0a_ioa_p0_2_sleep: tmr0a_ioa_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0b_cts_p0_2_sleep: uart0b_cts_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ext_clk_p0_3_sleep: ext_clk_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_ss0_p0_4_sleep: spi0a_ss0_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_ioan_p0_4_sleep: tmr0b_ioan_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_mosi_p0_5_sleep: spi0a_mosi_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_iobn_p0_5_sleep: tmr0b_iobn_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_miso_p0_6_sleep: spi0a_miso_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_6_sleep: owm_io_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_sck_p0_7_sleep: spi0a_sck_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_7_sleep: owm_pe_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_sdio2_p0_8_sleep: spi0a_sdio2_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_ioa_p0_8_sleep: tmr0b_ioa_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_sdio3_p0_9_sleep: spi0a_sdio3_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_iob_p0_9_sleep: tmr0b_iob_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_scl_p0_10_sleep: i2c0a_scl_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_ss2_p0_10_sleep: spi0b_ss2_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_sda_p0_11_sleep: i2c0a_sda_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_ss1_p0_11_sleep: spi0b_ss1_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rx_p0_12_sleep: uart1a_rx_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_ioa_p0_12_sleep: tmr1b_ioa_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_tx_p0_13_sleep: uart1a_tx_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_iobn_p0_13_sleep: tmr1b_iobn_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1a_ioa_p0_14_sleep: tmr1a_ioa_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_cts_p0_14_sleep: uart1b_cts_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1a_iob_p0_15_sleep: tmr1a_iob_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1b_rts_p0_15_sleep: uart1b_rts_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_scl_p0_16_sleep: i2c1a_scl_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2_p0_16_sleep: pt2_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_sda_p0_17_sleep: i2c1a_sda_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt3_p0_17_sleep: pt3_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_sdio2_p0_24_sleep: spi1a_sdio2_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2b_ioa_p0_24_sleep: tmr2b_ioa_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc0_rdy_p0_24_sleep: adc0_rdy_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_sdio3_p0_25_sleep: spi1a_sdio3_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2b_iob_p0_25_sleep: tmr2b_iob_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc1_rdy_p0_25_sleep: adc1_rdy_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2a_ioa_p0_26_sleep: tmr2a_ioa_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_ss1_p0_26_sleep: spi1b_ss1_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2a_iob_p0_27_sleep: tmr2a_iob_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_ss2_p0_27_sleep: spi1b_ss2_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swdio_p0_28_sleep: swdio_p0_28_sleep {
+		pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ swclk_p0_29_sleep: swclk_p0_29_sleep {
+		pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rx_p1_0_sleep: uart2a_rx_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tck_p1_0_sleep: rv_tck_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_tx_p1_1_sleep: uart2a_tx_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tms_p1_1_sleep: rv_tms_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_sck_p1_2_sleep: i2s0a_sck_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tdi_p1_2_sleep: rv_tdi_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_lrclk_p1_3_sleep: i2s0a_lrclk_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tdo_p1_3_sleep: rv_tdo_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_sdi_p1_4_sleep: i2s0a_sdi_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3b_ioa_p1_4_sleep: tmr3b_ioa_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0a_sdo_p1_5_sleep: i2s0a_sdo_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3b_iob_p1_5_sleep: tmr3b_iob_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3a_ioa_p1_6_sleep: tmr3a_ioa_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl2_p1_6_sleep: ble_ant_ctrl2_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3a_iob_p1_7_sleep: tmr3a_iob_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl3_p1_7_sleep: ble_ant_ctrl3_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain12_p2_4_sleep: ain12_p2_4_sleep {
+		pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_ioa_p2_4_sleep: lptmr0b_ioa_p2_4_sleep {
+		pinmux = <MAX32_PINMUX(2, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain13_p2_5_sleep: ain13_p2_5_sleep {
+		pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1b_ioa_p2_5_sleep: lptmr1b_ioa_p2_5_sleep {
+		pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0_clk_p2_6_sleep: lptmr0_clk_p2_6_sleep {
+		pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuartb_r_p2_6_sleep: lpuartb_r_p2_6_sleep {
+		pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ x_p2_6_sleep: x_p2_6_sleep {
+		pinmux = <MAX32_PINMUX(2, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1_clk_p2_7_sleep: lptmr1_clk_p2_7_sleep {
+		pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuartb_tx_p2_7_sleep: lpuartb_tx_p2_7_sleep {
+		pinmux = <MAX32_PINMUX(2, 7, AF2)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/arm/adi/max32/max32690-pinctrl.dtsi b/dts/arm/adi/max32/max32690-pinctrl.dtsi
index 60d3a148313..d682e42f52f 100644
--- a/dts/arm/adi/max32/max32690-pinctrl.dtsi
+++ b/dts/arm/adi/max32/max32690-pinctrl.dtsi
@@ -769,3 +769,955 @@
 		};
 	};
 };
+
+/* Low power modes pin state,
+ * user shall set related configurations like:
+ * pullup/pulldown, out/in...
+ * incase of their needs on the their target board
+ */
+&pinctrl {
+	/omit-if-no-ref/ spixr_sdio0_p0_1_sleep: spixr_sdio0_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sdio0_p0_1_sleep: spixf_sdio0_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2c_tx_p0_1_sleep: uart2c_tx_p0_1_sleep {
+		pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sdio2_p0_2_sleep: spixr_sdio2_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sdio2_p0_2_sleep: spixf_sdio2_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2c_cts_p0_2_sleep: uart2c_cts_p0_2_sleep {
+		pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sck_p0_3_sleep: spixr_sck_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sck_p0_3_sleep: spixf_sck_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2c_rts_p0_3_sleep: uart2c_rts_p0_3_sleep {
+		pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sdio3_p0_4_sleep: spixr_sdio3_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sdio3_p0_4_sleep: spixf_sdio3_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ioa_p0_4_sleep: tmr0c_ioa_p0_4_sleep {
+		pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_sdio1_p0_5_sleep: spixr_sdio1_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_sdio1_p0_5_sleep: spixf_sdio1_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_iob_p0_5_sleep: tmr2c_iob_p0_5_sleep {
+		pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixr_ss0_p0_6_sleep: spixr_ss0_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spixf_ss0_p0_6_sleep: spixf_ss0_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2c_rx_p0_6_sleep: uart2c_rx_p0_6_sleep {
+		pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p0_7_sleep: owm_pe_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_ioa_p0_7_sleep: tmr1b_ioa_p0_7_sleep {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p0_8_sleep: owm_io_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1b_iob_p0_8_sleep: tmr1b_iob_p0_8_sleep {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_clk_ext_p0_9_sleep: adc_clk_ext_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_ioan_p0_9_sleep: tmr0c_ioan_p0_9_sleep {
+		pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_a_p0_10_sleep: adc_trig_a_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0c_iobn_p0_10_sleep: tmr0c_iobn_p0_10_sleep {
+		pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_sda_p0_11_sleep: i2c1a_sda_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ioan_p0_11_sleep: tmr1c_ioan_p0_11_sleep {
+		pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_scl_p0_12_sleep: i2c1a_scl_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_iobn_p0_12_sleep: tmr1c_iobn_p0_12_sleep {
+		pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_ss1_p0_13_sleep: spi3a_ss1_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_ioa_p0_13_sleep: tmr0b_ioa_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2c_sda_p0_13_sleep: i2c2c_sda_p0_13_sleep {
+		pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_ss2_p0_14_sleep: spi3a_ss2_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr0b_iob_p0_14_sleep: tmr0b_iob_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2c_scl_p0_14_sleep: i2c2c_scl_p0_14_sleep {
+		pinmux = <MAX32_PINMUX(0, 14, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_sdio3_p0_15_sleep: spi3a_sdio3_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_ioa_p0_15_sleep: tmr1c_ioa_p0_15_sleep {
+		pinmux = <MAX32_PINMUX(0, 15, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_sck_p0_16_sleep: spi3a_sck_p0_16_sleep {
+		pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_sdio2_p0_17_sleep: spi3a_sdio2_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr1c_iob_p0_17_sleep: tmr1c_iob_p0_17_sleep {
+		pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_ss0_p0_19_sleep: spi3a_ss0_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tck_p0_19_sleep: rv_tck_p0_19_sleep {
+		pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_miso_p0_20_sleep: spi3a_miso_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tms_p0_20_sleep: rv_tms_p0_20_sleep {
+		pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi3a_mosi_p0_21_sleep: spi3a_mosi_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tdi_p0_21_sleep: rv_tdi_p0_21_sleep {
+		pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0a_ss0_p0_22_sleep: spi0a_ss0_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rv_tdo_p0_22_sleep: rv_tdo_p0_22_sleep {
+		pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt15_p0_23_sleep: pt15_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_clkext_p0_23_sleep: i2s0b_clkext_p0_23_sleep {
+		pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ rxev0_p0_24_sleep: rxev0_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_sck_p0_24_sleep: i2s0b_sck_p0_24_sleep {
+		pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ txevo_p0_25_sleep: txevo_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_sdi_p0_25_sleep: i2s0b_sdi_p0_25_sleep {
+		pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_sdo_p0_26_sleep: i2s0b_sdo_p0_26_sleep {
+		pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ erfo_clk_out_p0_27_sleep: erfo_clk_out_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0b_ws_p0_27_sleep: i2s0b_ws_p0_27_sleep {
+		pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_sda_p0_30_sleep: i2c0a_sda_p0_30_sleep {
+		pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_scl_p0_31_sleep: i2c0a_scl_p0_31_sleep {
+		pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_ss0_p1_0_sleep: spi4a_ss0_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_trig_b_p1_0_sleep: adc_trig_b_p1_0_sleep {
+		pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_mosi_p1_1_sleep: spi4a_mosi_p1_1_sleep {
+		pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_miso_p1_2_sleep: spi4a_miso_p1_2_sleep {
+		pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_sck_p1_3_sleep: spi4a_sck_p1_3_sleep {
+		pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_sdio2_p1_4_sleep: spi4a_sdio2_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2b_ioa_p1_4_sleep: tmr2b_ioa_p1_4_sleep {
+		pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_sdio3_p1_5_sleep: spi4a_sdio3_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2b_iob_p1_5_sleep: tmr2b_iob_p1_5_sleep {
+		pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_ss1_p1_6_sleep: spi4a_ss1_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt0_p1_6_sleep: pt0_p1_6_sleep {
+		pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_cts_p1_7_sleep: uart2a_cts_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt1_p1_7_sleep: pt1_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2c_sda_p1_7_sleep: i2c2c_sda_p1_7_sleep {
+		pinmux = <MAX32_PINMUX(1, 7, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rts_p1_8_sleep: uart2a_rts_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2_p1_8_sleep: pt2_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c2c_scl_p1_8_sleep: i2c2c_scl_p1_8_sleep {
+		pinmux = <MAX32_PINMUX(1, 8, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_rx_p1_9_sleep: uart2a_rx_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt3_p1_9_sleep: pt3_p1_9_sleep {
+		pinmux = <MAX32_PINMUX(1, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart2a_tx_p1_10_sleep: uart2a_tx_p1_10_sleep {
+		pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt4_p1_10_sleep: pt4_p1_10_sleep {
+		pinmux = <MAX32_PINMUX(1, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi4a_ss2_p1_11_sleep: spi4a_ss2_p1_11_sleep {
+		pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_cs0n_p1_11_sleep: hyp_cs0n_p1_11_sleep {
+		pinmux = <MAX32_PINMUX(1, 11, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt5_p1_12_sleep: pt5_p1_12_sleep {
+		pinmux = <MAX32_PINMUX(1, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d0_p1_12_sleep: hyp_d0_p1_12_sleep {
+		pinmux = <MAX32_PINMUX(1, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3a_ioa_p1_13_sleep: tmr3a_ioa_p1_13_sleep {
+		pinmux = <MAX32_PINMUX(1, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d4_p1_13_sleep: hyp_d4_p1_13_sleep {
+		pinmux = <MAX32_PINMUX(1, 13, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3a_iob_p1_14_sleep: tmr3a_iob_p1_14_sleep {
+		pinmux = <MAX32_PINMUX(1, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_rwds_p1_14_sleep: hyp_rwds_p1_14_sleep {
+		pinmux = <MAX32_PINMUX(1, 14, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d1_p1_15_sleep: hyp_d1_p1_15_sleep {
+		pinmux = <MAX32_PINMUX(1, 15, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d5_p1_16_sleep: hyp_d5_p1_16_sleep {
+		pinmux = <MAX32_PINMUX(1, 16, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt9_p1_17_sleep: pt9_p1_17_sleep {
+		pinmux = <MAX32_PINMUX(1, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_cs1n_p1_17_sleep: hyp_cs1n_p1_17_sleep {
+		pinmux = <MAX32_PINMUX(1, 17, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt6_p1_18_sleep: pt6_p1_18_sleep {
+		pinmux = <MAX32_PINMUX(1, 18, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d6_p1_18_sleep: hyp_d6_p1_18_sleep {
+		pinmux = <MAX32_PINMUX(1, 18, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt7_p1_19_sleep: pt7_p1_19_sleep {
+		pinmux = <MAX32_PINMUX(1, 19, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d2_p1_19_sleep: hyp_d2_p1_19_sleep {
+		pinmux = <MAX32_PINMUX(1, 19, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d3_p1_20_sleep: hyp_d3_p1_20_sleep {
+		pinmux = <MAX32_PINMUX(1, 20, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt8_p1_21_sleep: pt8_p1_21_sleep {
+		pinmux = <MAX32_PINMUX(1, 21, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ hyp_d7_p1_21_sleep: hyp_d7_p1_21_sleep {
+		pinmux = <MAX32_PINMUX(1, 21, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_ss0_p1_23_sleep: spi1a_ss0_p1_23_sleep {
+		pinmux = <MAX32_PINMUX(1, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_ss2_p1_24_sleep: spi1a_ss2_p1_24_sleep {
+		pinmux = <MAX32_PINMUX(1, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can0b_rx_p1_24_sleep: can0b_rx_p1_24_sleep {
+		pinmux = <MAX32_PINMUX(1, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_ss1_p1_25_sleep: spi1a_ss1_p1_25_sleep {
+		pinmux = <MAX32_PINMUX(1, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can0b_tx_p1_25_sleep: can0b_tx_p1_25_sleep {
+		pinmux = <MAX32_PINMUX(1, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_sck_p1_26_sleep: spi1a_sck_p1_26_sleep {
+		pinmux = <MAX32_PINMUX(1, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_ss2_p1_27_sleep: spi2a_ss2_p1_27_sleep {
+		pinmux = <MAX32_PINMUX(1, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_miso_p1_28_sleep: spi1a_miso_p1_28_sleep {
+		pinmux = <MAX32_PINMUX(1, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can1b_rx_p1_28_sleep: can1b_rx_p1_28_sleep {
+		pinmux = <MAX32_PINMUX(1, 28, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1a_mosi_p1_29_sleep: spi1a_mosi_p1_29_sleep {
+		pinmux = <MAX32_PINMUX(1, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can1b_tx_p1_29_sleep: can1b_tx_p1_29_sleep {
+		pinmux = <MAX32_PINMUX(1, 29, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_pe_p1_30_sleep: owm_pe_p1_30_sleep {
+		pinmux = <MAX32_PINMUX(1, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_sdio2_p1_30_sleep: spi1b_sdio2_p1_30_sleep {
+		pinmux = <MAX32_PINMUX(1, 30, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ owm_io_p1_31_sleep: owm_io_p1_31_sleep {
+		pinmux = <MAX32_PINMUX(1, 31, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi1b_sdio3_p1_31_sleep: spi1b_sdio3_p1_31_sleep {
+		pinmux = <MAX32_PINMUX(1, 31, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_ss1_p2_1_sleep: spi2a_ss1_p2_1_sleep {
+		pinmux = <MAX32_PINMUX(2, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt10_p2_1_sleep: pt10_p2_1_sleep {
+		pinmux = <MAX32_PINMUX(2, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_sck_p2_2_sleep: spi2a_sck_p2_2_sleep {
+		pinmux = <MAX32_PINMUX(2, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_miso_p2_3_sleep: spi2a_miso_p2_3_sleep {
+		pinmux = <MAX32_PINMUX(2, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_mosi_p2_4_sleep: spi2a_mosi_p2_4_sleep {
+		pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2a_ss0_p2_5_sleep: spi2a_ss0_p2_5_sleep {
+		pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt11_p2_5_sleep: pt11_p2_5_sleep {
+		pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2b_sdio2_p2_6_sleep: spi2b_sdio2_p2_6_sleep {
+		pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_sda_p2_7_sleep: i2c0a_sda_p2_7_sleep {
+		pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi2b_sdio3_p2_7_sleep: spi2b_sdio3_p2_7_sleep {
+		pinmux = <MAX32_PINMUX(2, 7, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c0a_scl_p2_8_sleep: i2c0a_scl_p2_8_sleep {
+		pinmux = <MAX32_PINMUX(2, 8, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_cts_p2_9_sleep: uart0a_cts_p2_9_sleep {
+		pinmux = <MAX32_PINMUX(2, 9, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt12_p2_9_sleep: pt12_p2_9_sleep {
+		pinmux = <MAX32_PINMUX(2, 9, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rts_p2_10_sleep: uart0a_rts_p2_10_sleep {
+		pinmux = <MAX32_PINMUX(2, 10, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt14_p2_10_sleep: pt14_p2_10_sleep {
+		pinmux = <MAX32_PINMUX(2, 10, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_rx_p2_11_sleep: uart0a_rx_p2_11_sleep {
+		pinmux = <MAX32_PINMUX(2, 11, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt13_p2_11_sleep: pt13_p2_11_sleep {
+		pinmux = <MAX32_PINMUX(2, 11, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart0a_tx_p2_12_sleep: uart0a_tx_p2_12_sleep {
+		pinmux = <MAX32_PINMUX(2, 12, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt15_p2_12_sleep: pt15_p2_12_sleep {
+		pinmux = <MAX32_PINMUX(2, 12, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_cts_p2_13_sleep: uart1a_cts_p2_13_sleep {
+		pinmux = <MAX32_PINMUX(2, 13, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rx_p2_14_sleep: uart1a_rx_p2_14_sleep {
+		pinmux = <MAX32_PINMUX(2, 14, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_rts_p2_15_sleep: uart1a_rts_p2_15_sleep {
+		pinmux = <MAX32_PINMUX(2, 15, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ adc_hw_trig_c_p2_15_sleep: adc_hw_trig_c_p2_15_sleep {
+		pinmux = <MAX32_PINMUX(2, 15, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ uart1a_tx_p2_16_sleep: uart1a_tx_p2_16_sleep {
+		pinmux = <MAX32_PINMUX(2, 16, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_sda_p2_17_sleep: i2c1a_sda_p2_17_sleep {
+		pinmux = <MAX32_PINMUX(2, 17, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl1_p2_17_sleep: ble_ant_ctrl1_p2_17_sleep {
+		pinmux = <MAX32_PINMUX(2, 17, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2c1a_scl_p2_18_sleep: i2c1a_scl_p2_18_sleep {
+		pinmux = <MAX32_PINMUX(2, 18, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl0_p2_18_sleep: ble_ant_ctrl0_p2_18_sleep {
+		pinmux = <MAX32_PINMUX(2, 18, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt5_p2_20_sleep: pt5_p2_20_sleep {
+		pinmux = <MAX32_PINMUX(2, 20, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl2_p2_20_sleep: ble_ant_ctrl2_p2_20_sleep {
+		pinmux = <MAX32_PINMUX(2, 20, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_ioa_p2_20_sleep: tmr2c_ioa_p2_20_sleep {
+		pinmux = <MAX32_PINMUX(2, 20, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt7_p2_21_sleep: pt7_p2_21_sleep {
+		pinmux = <MAX32_PINMUX(2, 21, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ble_ant_ctrl3_p2_21_sleep: ble_ant_ctrl3_p2_21_sleep {
+		pinmux = <MAX32_PINMUX(2, 21, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr2c_iob_p2_21_sleep: tmr2c_iob_p2_21_sleep {
+		pinmux = <MAX32_PINMUX(2, 21, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt8_p2_22_sleep: pt8_p2_22_sleep {
+		pinmux = <MAX32_PINMUX(2, 22, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can0b_rx_p2_22_sleep: can0b_rx_p2_22_sleep {
+		pinmux = <MAX32_PINMUX(2, 22, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt6_p2_23_sleep: pt6_p2_23_sleep {
+		pinmux = <MAX32_PINMUX(2, 23, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can0b_tx_p2_23_sleep: can0b_tx_p2_23_sleep {
+		pinmux = <MAX32_PINMUX(2, 23, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt10_p2_24_sleep: pt10_p2_24_sleep {
+		pinmux = <MAX32_PINMUX(2, 24, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can1b_rx_p2_24_sleep: can1b_rx_p2_24_sleep {
+		pinmux = <MAX32_PINMUX(2, 24, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt11_p2_25_sleep: pt11_p2_25_sleep {
+		pinmux = <MAX32_PINMUX(2, 25, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ can1b_tx_p2_25_sleep: can1b_tx_p2_25_sleep {
+		pinmux = <MAX32_PINMUX(2, 25, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt12_p2_26_sleep: pt12_p2_26_sleep {
+		pinmux = <MAX32_PINMUX(2, 26, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_ss1_p2_26_sleep: spi0b_ss1_p2_26_sleep {
+		pinmux = <MAX32_PINMUX(2, 26, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0c_ws_p2_26_sleep: i2s0c_ws_p2_26_sleep {
+		pinmux = <MAX32_PINMUX(2, 26, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt13_p2_27_sleep: pt13_p2_27_sleep {
+		pinmux = <MAX32_PINMUX(2, 27, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_miso_p2_27_sleep: spi0b_miso_p2_27_sleep {
+		pinmux = <MAX32_PINMUX(2, 27, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0c_sdi_p2_27_sleep: i2s0c_sdi_p2_27_sleep {
+		pinmux = <MAX32_PINMUX(2, 27, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt14_p2_28_sleep: pt14_p2_28_sleep {
+		pinmux = <MAX32_PINMUX(2, 28, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_mosi_p2_28_sleep: spi0b_mosi_p2_28_sleep {
+		pinmux = <MAX32_PINMUX(2, 28, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0c_sdo_p2_28_sleep: i2s0c_sdo_p2_28_sleep {
+		pinmux = <MAX32_PINMUX(2, 28, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt0_p2_29_sleep: pt0_p2_29_sleep {
+		pinmux = <MAX32_PINMUX(2, 29, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_sck_p2_29_sleep: spi0b_sck_p2_29_sleep {
+		pinmux = <MAX32_PINMUX(2, 29, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ i2s0c_sck_p2_29_sleep: i2s0c_sck_p2_29_sleep {
+		pinmux = <MAX32_PINMUX(2, 29, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt1_p2_30_sleep: pt1_p2_30_sleep {
+		pinmux = <MAX32_PINMUX(2, 30, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_sdio2_p2_30_sleep: spi0b_sdio2_p2_30_sleep {
+		pinmux = <MAX32_PINMUX(2, 30, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_ioa_p2_30_sleep: tmr3c_ioa_p2_30_sleep {
+		pinmux = <MAX32_PINMUX(2, 30, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ pt2_p2_31_sleep: pt2_p2_31_sleep {
+		pinmux = <MAX32_PINMUX(2, 31, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ spi0b_sdio3_p2_31_sleep: spi0b_sdio3_p2_31_sleep {
+		pinmux = <MAX32_PINMUX(2, 31, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ tmr3c_iob_p2_31_sleep: tmr3c_iob_p2_31_sleep {
+		pinmux = <MAX32_PINMUX(2, 31, AF3)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain0_p3_0_sleep: ain0_p3_0_sleep {
+		pinmux = <MAX32_PINMUX(3, 0, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0b_rx_p3_0_sleep: lpuart0b_rx_p3_0_sleep {
+		pinmux = <MAX32_PINMUX(3, 0, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain1_p3_1_sleep: ain1_p3_1_sleep {
+		pinmux = <MAX32_PINMUX(3, 1, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0b_tx_p3_1_sleep: lpuart0b_tx_p3_1_sleep {
+		pinmux = <MAX32_PINMUX(3, 1, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain2_p3_2_sleep: ain2_p3_2_sleep {
+		pinmux = <MAX32_PINMUX(3, 2, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0b_cts_p3_2_sleep: lpuart0b_cts_p3_2_sleep {
+		pinmux = <MAX32_PINMUX(3, 2, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain3_p3_3_sleep: ain3_p3_3_sleep {
+		pinmux = <MAX32_PINMUX(3, 3, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lpuart0b_rts_p3_3_sleep: lpuart0b_rts_p3_3_sleep {
+		pinmux = <MAX32_PINMUX(3, 3, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain4_p3_4_sleep: ain4_p3_4_sleep {
+		pinmux = <MAX32_PINMUX(3, 4, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr0b_ioa_p3_4_sleep: lptmr0b_ioa_p3_4_sleep {
+		pinmux = <MAX32_PINMUX(3, 4, AF2)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain5_p3_5_sleep: ain5_p3_5_sleep {
+		pinmux = <MAX32_PINMUX(3, 5, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain6_p3_6_sleep: ain6_p3_6_sleep {
+		pinmux = <MAX32_PINMUX(3, 6, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ ain7_p3_7_sleep: ain7_p3_7_sleep {
+		pinmux = <MAX32_PINMUX(3, 7, AF1)>;
+		low-power-enable;
+	};
+
+	/omit-if-no-ref/ lptmr1b_ioa_p3_7_sleep: lptmr1b_ioa_p3_7_sleep {
+		pinmux = <MAX32_PINMUX(3, 7, AF2)>;
+		low-power-enable;
+	};
+};
diff --git a/dts/bindings/pinctrl/adi,max32-pinctrl.yaml b/dts/bindings/pinctrl/adi,max32-pinctrl.yaml
index 414983eb1a9..71260060921 100644
--- a/dts/bindings/pinctrl/adi,max32-pinctrl.yaml
+++ b/dts/bindings/pinctrl/adi,max32-pinctrl.yaml
@@ -32,6 +32,7 @@ child-binding:
         - output-enable
         - power-source
         - drive-strength
+        - low-power-enable
 
   properties:
     pinmux: