arm: exx32: Add Silabs EFR32FG1P soc files

The Silicon Labs EFR32FG1 Flex Gecko MCU includes:
	* Cortex-M4F core at 40MHz
	* up to 256KB of flash and 32KB of RAM
	* integrated Sub-GHz and/or 2.4GHz radio
	* multiple low power peripherals

Signed-off-by: Christian Taedcke <hacking@taedcke.com>

arch/arm/soc/silabs_exx32/Kconfig

@@ -18,6 +18,7 @@ gsource "arch/arm/soc/silabs_exx32/*/Kconfig.soc"
 config SOC_PART_NUMBER
 	string
 	default SOC_PART_NUMBER_EXX32_EFM32WG   if SOC_SERIES_EFM32WG
+	default SOC_PART_NUMBER_EXX32_EFR32FG1P if SOC_SERIES_EFR32FG1P
 	help
 	  This string holds the full part number of the SoC. It is a hidden option
 	  that you should not set directly. The part number selection choice defines

arch/arm/soc/silabs_exx32/efr32fg1p/CMakeLists.txt

@@ -0,0 +1 @@
+zephyr_sources(soc.c)

arch/arm/soc/silabs_exx32/efr32fg1p/Kconfig.defconfig.efr32fg1p

@@ -0,0 +1,32 @@
+# Kconfig - Silicon Labs EFR32FG1P platform configuration options
+
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EFR32FG1P
+
+config SOC
+	string
+	default "efr32fg1p"
+
+config GPIO
+	def_bool y
+
+if GPIO
+
+config GPIO_GECKO
+	def_bool y
+
+endif # GPIO
+
+if SERIAL
+
+config UART_GECKO
+	def_bool y
+
+endif # SERIAL
+
+endif # SOC_EFR32FG1P

arch/arm/soc/silabs_exx32/efr32fg1p/Kconfig.defconfig.series

@@ -0,0 +1,21 @@
+# Kconfig - EFR32FG1P series configuration options
+
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_EFR32FG1P
+
+config SOC_SERIES
+	default "efr32fg1p"
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 33
+
+gsource "arch/arm/soc/silabs_exx32/efr32fg1p/Kconfig.defconfig.e*"
+
+endif # SOC_SERIES_EFR32FG1P

arch/arm/soc/silabs_exx32/efr32fg1p/Kconfig.series

@@ -0,0 +1,17 @@
+# Kconfig - EFR32FG1P MCU line
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_EFR32FG1P
+	bool "EFR32FG1P Series MCU"
+	select HAS_SILABS_GECKO
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select SOC_FAMILY_EXX32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select CPU_HAS_SYSTICK
+	help
+	  Enable support for EFR32 FlexGecko MCU series

arch/arm/soc/silabs_exx32/efr32fg1p/Kconfig.soc

@@ -0,0 +1,31 @@
+# Kconfig - EFR32FG1P MCU line
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "EFR32FG1P Flex Gecko MCU Selection"
+depends on SOC_SERIES_EFR32FG1P
+
+config SOC_EFR32FG1P
+	bool "SOC_EFR32FG1P"
+	select HAS_CMU
+
+endchoice
+
+if SOC_SERIES_EFR32FG1P
+
+config SOC_PART_NUMBER_EFR32FG1P133F256GM48
+	bool
+
+config SOC_PART_NUMBER_EXX32_EFR32FG1P
+	string
+	default "EFR32FG1P133F256GM48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.
+
+endif # SOC_SERIES_EFR32FG1P

arch/arm/soc/silabs_exx32/efr32fg1p/dts.fixup

@@ -0,0 +1,15 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+#define CONFIG_USART_GECKO_0_NAME	SILABS_EFM32_USART_40010000_LABEL
+
+#define CONFIG_USART_GECKO_0_BAUD_RATE	SILABS_EFM32_USART_40010000_CURRENT_SPEED
+#define CONFIG_USART_GECKO_0_IRQ_PRI	SILABS_EFM32_USART_40010000_IRQ_0_PRIORITY
+
+/* End of SoC Level DTS fixup file */

arch/arm/soc/silabs_exx32/efr32fg1p/linker.ld

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images.
+ */
+
+#include <autoconf.h>
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/silabs_exx32/efr32fg1p/soc.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018, Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SoC initialization for the EFR32FG1P
+ */
+
+#include <kernel.h>
+#include <init.h>
+#include <soc.h>
+#include <em_cmu.h>
+#include <em_chip.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+#ifdef CONFIG_CMU_HFCLK_HFXO
+/**
+ * @brief Initialization parameters for the external high frequency oscillator
+ */
+static const CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT;
+#elif (defined CONFIG_CMU_HFCLK_LFXO)
+/**
+ * @brief Initialization parameters for the external low frequency oscillator
+ */
+static const CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT;
+#endif
+
+/**
+ * @brief Initialize the system clock
+ *
+ * @return N/A
+ *
+ */
+static ALWAYS_INLINE void clkInit(void)
+{
+#ifdef CONFIG_CMU_HFCLK_HFXO
+	CMU_HFXOInit(&hfxoInit);
+	CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+	CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
+	CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
+	SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ);
+#elif (defined CONFIG_CMU_HFCLK_LFXO)
+	CMU_LFXOInit(&lfxoInit);
+	CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
+	CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO);
+	CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
+	SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ);
+#elif (defined CONFIG_CMU_HFCLK_HFRCO)
+	/*
+	 * This is the default clock, the controller starts with, so nothing to
+	 * do here.
+	 */
+#else
+#error "Unsupported clock source for HFCLK selected"
+#endif
+
+	/* Enable the High Frequency Peripheral Clock */
+	CMU_ClockEnable(cmuClock_HFPER, true);
+
+#ifdef CONFIG_GPIO_GECKO
+	CMU_ClockEnable(cmuClock_GPIO, true);
+#endif
+}
+
+/**
+ * @brief Perform basic hardware initialization
+ *
+ * Initialize the interrupt controller device drivers.
+ * Also initialize the timer device driver, if required.
+ *
+ * @return 0
+ */
+static int silabs_efr32fg1p_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	int oldLevel; /* old interrupt lock level */
+
+	/* disable interrupts */
+	oldLevel = irq_lock();
+
+	/* handle chip errata */
+	CHIP_Init();
+
+	_ClearFaults();
+
+	/* Initialize system clock according to CONFIG_CMU settings */
+	clkInit();
+
+	/*
+	 * install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	/* restore interrupt state */
+	irq_unlock(oldLevel);
+	return 0;
+}
+
+SYS_INIT(silabs_efr32fg1p_init, PRE_KERNEL_1, 0);

arch/arm/soc/silabs_exx32/efr32fg1p/soc.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the efr32fg1p soc
+ *
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <misc/util.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+
+#include <em_bus.h>
+#include <em_common.h>
+#include <device.h>
+
+#include "soc_pinmap.h"
+#include "../common/soc_gpio.h"
+
+#endif /* !_ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC__H_ */

arch/arm/soc/silabs_exx32/efr32fg1p/soc_pinmap.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief Silabs EFR32FG1P MCU pin definitions.
+ *
+ * This file contains pin configuration data required by different MCU
+ * modules to correctly configure GPIO controller.
+ */
+
+#ifndef _SILABS_EFR32FG1P_SOC_PINMAP_H_
+#define _SILABS_EFR32FG1P_SOC_PINMAP_H_
+
+#include <soc.h>
+#include <em_gpio.h>
+
+#ifdef CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48
+#ifdef CONFIG_USART_GECKO_0
+#if (CONFIG_USART_GECKO_0_GPIO_LOC == 0)
+#define PIN_USART0_TXD {gpioPortA, 0, gpioModePushPull, 1}
+#define PIN_USART0_RXD {gpioPortA, 1, gpioModeInput, 1}
+#elif (CONFIG_USART_GECKO_0_GPIO_LOC == 1)
+#define PIN_USART0_TXD {gpioPortA, 1, gpioModePushPull, 1}
+#define PIN_USART0_RXD {gpioPortA, 2, gpioModeInput, 1}
+#elif (CONFIG_USART_GECKO_0_GPIO_LOC == 2)
+#define PIN_USART0_TXD {gpioPortA, 2, gpioModePushPull, 1}
+#define PIN_USART0_RXD {gpioPortA, 3, gpioModeInput, 1}
+#else
+#error ("Serial Driver for Gecko MCUs not implemented for this location index")
+#endif
+#endif /* CONFIG_USART_GECKO_0 */
+
+#ifdef CONFIG_USART_GECKO_1
+#if (CONFIG_USART_GECKO_1_GPIO_LOC == 0)
+#error ("Serial Driver for Gecko MCUs not implemented for this location index")
+#elif (CONFIG_USART_GECKO_1_GPIO_LOC == 1)
+#define PIN_USART1_TXD {gpioPortF, 10, gpioModePushPull, 1}
+#define PIN_USART1_RXD {gpioPortF, 11, gpioModeInput, 1}
+#elif (CONFIG_USART_GECKO_1_GPIO_LOC == 2)
+#define PIN_USART1_TXD {gpioPortB, 9, gpioModePushPull, 1}
+#define PIN_USART1_RXD {gpioPortB, 10, gpioModeInput, 1}
+#elif (CONFIG_USART_GECKO_1_GPIO_LOC == 3)
+#define PIN_USART1_TXD {gpioPortE, 2, gpioModePushPull, 1}
+#define PIN_USART1_RXD {gpioPortE, 3, gpioModeInput, 1}
+#else
+#error ("Serial Driver for Gecko MCUs not implemented for this location index")
+#endif
+#endif /* CONFIG_USART_GECKO_1 */
+#else
+#error ("Pinmap not available for this for Flex Gecko MCU")
+#endif /* CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48 */
+
+#endif /* _SILABS_EFR32FG1P_SOC_PINMAP_H_ */