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soc: st: stm32h7rs serie requires specific power rails

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Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2024-10-01 11:57:21 +02:00 • committed by Anas Nashif
commit 48a2aedb78
1 changed files with 10 additions and 0 deletions
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10
soc/st/stm32/stm32h7rsx/soc.c
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@ -68,4 +68,14 @@ void soc_early_init_hook(void)
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
while (LL_PWR_IsActiveFlag_VOSRDY() == 0) { while (LL_PWR_IsActiveFlag_VOSRDY() == 0) {
} }
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioo), okay) || DT_NODE_HAS_STATUS(DT_NODELABEL(gpiop), okay)
LL_PWR_EnableXSPIM1(); /* Required for powering GPIO O and P */
#endif /* gpioo || gpio p */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpion), okay)
LL_PWR_EnableXSPIM2(); /* Required for powering GPIO N */
#endif /* gpio n */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiom), okay)
LL_PWR_EnableUSBVoltageDetector(); /* Required for powering GPIO M */
#endif /* gpiom */
} }