From 488526190fa5ff54086614f1ff880ba1127834a7 Mon Sep 17 00:00:00 2001 From: Alvis Sun Date: Fri, 28 Mar 2025 14:01:19 +0800 Subject: [PATCH] dts: arm: npcx: Add dts files for NPCK3 series K3 series is a Nuvoton embedded controller based on NPCX series. Add npck3m8k dtsi Signed-off-by: Alvis Sun Signed-off-by: Mulin Chao --- dts/arm/nuvoton/npck/npck-alts-map.dtsi | 573 +++++++++++++++ dts/arm/nuvoton/npck/npck-espi-vws-map.dtsi | 155 ++++ dts/arm/nuvoton/npck/npck-lvol-ctrl-map.dtsi | 164 +++++ dts/arm/nuvoton/npck/npck-miwus-int-map.dtsi | 169 +++++ dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi | 608 +++++++++++++++ dts/arm/nuvoton/npck/npck.dtsi | 693 ++++++++++++++++++ dts/arm/nuvoton/npck/npck3.dtsi | 269 +++++++ .../nuvoton/npck/npck3/npck3-alts-map.dtsi | 15 + .../npck/npck3/npck3-espi-vws-map.dtsi | 10 + .../npck/npck3/npck3-lvol-ctrl-map.dtsi | 15 + .../npck/npck3/npck3-miwus-int-map.dtsi | 15 + .../npck/npck3/npck3-miwus-wui-map.dtsi | 16 + dts/arm/nuvoton/npck/npck3/npck3-pinctrl.dtsi | 407 ++++++++++ dts/arm/nuvoton/npck3m8k.dtsi | 33 + 14 files changed, 3142 insertions(+) create mode 100644 dts/arm/nuvoton/npck/npck-alts-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck-espi-vws-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck-lvol-ctrl-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck-miwus-int-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3/npck3-alts-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3/npck3-espi-vws-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3/npck3-lvol-ctrl-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3/npck3-miwus-wui-map.dtsi create mode 100644 dts/arm/nuvoton/npck/npck3/npck3-pinctrl.dtsi create mode 100644 dts/arm/nuvoton/npck3m8k.dtsi diff --git a/dts/arm/nuvoton/npck/npck-alts-map.dtsi b/dts/arm/nuvoton/npck/npck-alts-map.dtsi new file mode 100644 index 00000000000..e702ef1b541 --- /dev/null +++ b/dts/arm/nuvoton/npck/npck-alts-map.dtsi @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + npcx-alts-map { + compatible = "nuvoton,npcx-pinctrl-conf"; + + /* SCFG device alternative table */ + /* SCFG DEVALT 0 */ + alt0_sp1i_sl: alt00 { + alts = <&scfg 0x00 0x0 0>; + }; + + alt0_sp1o_sl: alt01 { + alts = <&scfg 0x00 0x1 0>; + }; + + alt0_ckout_sl: alt02 { + alts = <&scfg 0x00 0x2 0>; + }; + + alt0_spip1_sl: alt03 { + alts = <&scfg 0x00 0x3 0>; + }; + + alt0_sp2ctl_sl: alt04 { + alts = <&scfg 0x00 0x4 0>; + }; + + alt0_pvt_spi_sl: alt05 { + alts = <&scfg 0x00 0x5 0>; + }; + + alt0_shd_bkp_spi_sl: alt05-inv { + alts = <&scfg 0x00 0x5 1>; + }; + + alt0_shdf_spi_quad: alt06 { + alts = <&scfg 0x00 0x6 0>; + }; + + alt0_shd1_spi: alt07 { + alts = <&scfg 0x00 0x7 0>; + }; + + /* SCFG DEVALT 1 */ + alt1_ovt_sl: alt10 { + alts = <&scfg 0x01 0x0 0>; + }; + + alt1_urti_sl: alt11 { + alts = <&scfg 0x01 0x1 0>; + }; + + alt1_urto1_sl: alt12 { + alts = <&scfg 0x01 0x2 0>; + }; + + alt1_sp1ctl_sl: alt14 { + alts = <&scfg 0x01 0x4 0>; + }; + + alt1_dpwrok_sl_def: alt15 { + alts = <&scfg 0x01 0x5 0>; + }; + + alt1_vcc_pwrgd_sl_def: alt16 { + alts = <&scfg 0x01 0x6 0>; + }; + + alt1_lpc_espi_def: alt17 { + alts = <&scfg 0x01 0x7 0>; + }; + + /* SCFG DEVALT 2 */ + alt2_lpcpd_sl: alt21 { + alts = <&scfg 0x02 0x1 0>; + }; + + alt2_clkrun_sl: alt22 { + alts = <&scfg 0x02 0x2 0>; + }; + + alt2_smi_sl: alt23 { + alts = <&scfg 0x02 0x3 0>; + }; + + alt2_serirq_sl: alt24 { + alts = <&scfg 0x02 0x4 0>; + }; + + alt2_ecsci_sl_def: alt25 { + alts = <&scfg 0x02 0x5 0>; + }; + + alt2_smb1a_sl: alt26 { + alts = <&scfg 0x02 0x6 0>; + }; + + alt2_smb1b_sl: alt27 { + alts = <&scfg 0x02 0x7 0>; + }; + + /* SCFG DEVALT 3 */ + alt3_ta1_1_sl: alt30 { + alts = <&scfg 0x03 0x0 0>; + }; + + alt3_ta2_1_sl: alt31 { + alts = <&scfg 0x03 0x1 0>; + }; + + alt3_tb1_1_sl: alt32 { + alts = <&scfg 0x03 0x2 0>; + }; + + alt3_tb2_1_sl: alt33 { + alts = <&scfg 0x03 0x3 0>; + }; + + alt3_ta3_1_sl: alt34 { + alts = <&scfg 0x03 0x4 0>; + }; + + alt3_tb3_1_sl: alt35 { + alts = <&scfg 0x03 0x5 0>; + }; + + alt3_tb1_2_sl: alt36 { + alts = <&scfg 0x03 0x6 0>; + }; + + alt3_ta1_2_sl: alt37 { + alts = <&scfg 0x03 0x7 0>; + }; + + /* SCFG DEVALT 4 */ + alt4_shd2_spi: alt40 { + alts = <&scfg 0x04 0x0 0>; + }; + + alt4_noshd2_spi: alt40-inv { + alts = <&scfg 0x04 0x0 1>; + }; + + alt4_ckout2_sl: alt41 { + alts = <&scfg 0x04 0x1 0>; + }; + + alt4_clk24m_in2_sl: alt42 { + alts = <&scfg 0x04 0x2 0>; + }; + + alt4_clk24m_in1_sl: alt43 { + alts = <&scfg 0x04 0x3 0>; + }; + + alt4_ps2_3_sl: alt44 { + alts = <&scfg 0x04 0x4 0>; + }; + + alt4_ps2_2_sl: alt46 { + alts = <&scfg 0x04 0x6 0>; + }; + + /* SCFG DEVALT 5 */ + alt5_a_pwm_sl: alt50 { + alts = <&scfg 0x05 0x0 0>; + }; + + alt5_b_pwm_sl: alt51 { + alts = <&scfg 0x05 0x1 0>; + }; + + alt5_c_pwm_sl: alt52 { + alts = <&scfg 0x05 0x2 0>; + }; + + alt5_d_pwm_sl: alt53 { + alts = <&scfg 0x05 0x3 0>; + }; + + alt5_f_pwm_sl: alt55 { + alts = <&scfg 0x05 0x5 0>; + }; + + /* SCFG DEVALT 6 */ + alt6_adc0_sl: alt60 { + alts = <&scfg 0x06 0x0 0>; + }; + + alt6_adc1_sl: alt61 { + alts = <&scfg 0x06 0x1 0>; + }; + + alt6_adc2_sl: alt62 { + alts = <&scfg 0x06 0x2 0>; + }; + + alt6_adc3_sl: alt63 { + alts = <&scfg 0x06 0x3 0>; + }; + + alt6_adc4_sl: alt64 { + alts = <&scfg 0x06 0x4 0>; + }; + + alt6_adc5_sl: alt65 { + alts = <&scfg 0x06 0x5 0>; + }; + + alt6_adc6_sl: alt66 { + alts = <&scfg 0x06 0x6 0>; + }; + + alt6_adc7_sl: alt67 { + alts = <&scfg 0x06 0x7 0>; + }; + + /* SCFG DEVALT 7 */ + alt7_kso12_sl_def: alt72 { + alts = <&scfg 0x07 0x2 0>; + }; + + alt7_kso13_sl_def: alt73 { + alts = <&scfg 0x07 0x3 0>; + }; + + alt7_kso14_sl_def: alt74 { + alts = <&scfg 0x07 0x4 0>; + }; + + alt7_kso15_sl_def: alt75 { + alts = <&scfg 0x07 0x5 0>; + }; + + alt7_kso16_sl: alt76 { + alts = <&scfg 0x07 0x6 0>; + }; + + alt7_kso17_sl: alt77 { + alts = <&scfg 0x07 0x7 0>; + }; + + /* SCFG DEVALT 8 */ + alt8_ga20_sl: alt81 { + alts = <&scfg 0x08 0x1 0>; + }; + + alt8_kbrst_sl_def: alt82 { + alts = <&scfg 0x08 0x2 0>; + }; + + alt8_k_pwm_sl: alt85 { + alts = <&scfg 0x08 0x5 0>; + }; + + alt8_j_pwm_sl: alt86 { + alts = <&scfg 0x08 0x6 0>; + }; + + alt8_i_pwm_sl: alt87 { + alts = <&scfg 0x08 0x7 0>; + }; + + /* SCFG DEVALT 9 */ + alt9_no_ksi0_ksi1_ksi2_ksi3_sl: alt90-inv { + alts = <&scfg 0x09 0x0 1>; + }; + + alt9_no_ksi4_ksi5_sl: alt92-inv { + alts = <&scfg 0x09 0x2 1>; + }; + + alt9_no_ksi6_ksi7_sl: alt93-inv { + alts = <&scfg 0x09 0x3 1>; + }; + + alt9_no_kso0_kso1_kso2_kso3_sl: alt94-inv { + alts = <&scfg 0x09 0x4 1>; + }; + + alt9_no_kso4_kso5_kso6_kso7_sl: alt95-inv { + alts = <&scfg 0x09 0x5 1>; + }; + + alt9_no_kso8_kso9_sl: alt96-inv { + alts = <&scfg 0x09 0x6 1>; + }; + + alt9_no_kso10_kso11_sl: alt97-inv { + alts = <&scfg 0x09 0x7 1>; + }; + + /* SCFG DEVALT A */ + alta_shi_sl: alta0 { + alts = <&scfg 0x0a 0x0 0>; + }; + + alta_smb6a_sl: alta1 { + alts = <&scfg 0x0a 0x1 0>; + }; + + alta_smb5a_sl: alta2 { + alts = <&scfg 0x0a 0x2 0>; + }; + + alta_13c1a_sl: alta4 { + alts = <&scfg 0x0a 0x4 0>; + }; + + alta_13c1b_sl: alta5 { + alts = <&scfg 0x0a 0x5 0>; + }; + + alta_smb3a_sl: alta6 { + alts = <&scfg 0x0a 0x6 0>; + }; + + alta_smb4a_sl: alta7 { + alts = <&scfg 0x0a 0x7 0>; + }; + + /* SCFG DEVALT B */ + altb_sp2i_sl: altb0 { + alts = <&scfg 0x0b 0x0 0>; + }; + + altb_sp2o_sl: altb1 { + alts = <&scfg 0x0b 0x1 0>; + }; + + altb_ri1_sl: altb2 { + alts = <&scfg 0x0b 0x2 0>; + }; + + altb_cts1_sl: altb3 { + alts = <&scfg 0x0b 0x3 0>; + }; + + altb_rts1_sl: altb4 { + alts = <&scfg 0x0b 0x4 0>; + }; + + altb_ri2_sl: altb5 { + alts = <&scfg 0x0b 0x5 0>; + }; + + altb_cts2_sl: altb6 { + alts = <&scfg 0x0b 0x6 0>; + }; + + altb_rts2_sl: altb7 { + alts = <&scfg 0x0b 0x7 0>; + }; + + /* SCFG DEVALT C */ + altc_smb4b_sl: altc4 { + alts = <&scfg 0x0C 0x4 0>; + }; + + altc_smb3b_sl: altc5 { + alts = <&scfg 0x0C 0x5 0>; + }; + + altc_smb2b_sl: altc6 { + alts = <&scfg 0x0C 0x6 0>; + }; + + altc_smb2a_sl: altc7 { + alts = <&scfg 0x0C 0x7 0>; + }; + + /* SCFG DEVALT D */ + altd_gpstby0_out_in_sby: altd0 { + alts = <&scfg 0x0d 0x0 0>; + }; + + altd_gpstby1_out_in_sby: altd1 { + alts = <&scfg 0x0d 0x1 0>; + }; + + altd_psl_in0_en_out_def: altd2 { + alts = <&scfg 0x0d 0x2 0>; + }; + + altd_psl_in1_en_out_def: altd3 { + alts = <&scfg 0x0d 0x3 0>; + }; + + altd_psl_in2_en_out_def: altd4 { + alts = <&scfg 0x0d 0x4 0>; + }; + + altd_psl_in3_en_out_def: altd5 { + alts = <&scfg 0x0d 0x5 0>; + }; + + altd_psl_in4_en_out_def: altd6 { + alts = <&scfg 0x0d 0x6 0>; + }; + + altd_psl_in5_en_out_def: altd7 { + alts = <&scfg 0x0d 0x7 0>; + }; + + /* SCFG DEVALT E */ + alte_spip2_sl: alte5 { + alts = <&scfg 0x0e 0x5 0>; + }; + + /* SCFG DEVALT F */ + altf_psl_in0_en_def: altf1 { + alts = <&scfg 0x0f 0x1 0>; + }; + + altf_psl_in1_en_def: altf2 { + alts = <&scfg 0x0f 0x2 0>; + }; + + altf_psl_in2_en: altf3 { + alts = <&scfg 0x0f 0x3 0>; + }; + + altf_psl_in3_en: altf4 { + alts = <&scfg 0x0f 0x4 0>; + }; + + altf_psl_in4_en: altf5 { + alts = <&scfg 0x0f 0x5 0>; + }; + + altf_psl_in5_en: altf6 { + alts = <&scfg 0x0f 0x6 0>; + }; + + altf_psl_out_en_def: altf7 { + alts = <&scfg 0x0f 0x7 0>; + }; + + /* SCFG DEVALT 10 */ + alt10_tb5_sl: alt100 { + alts = <&scfg 0x10 0x0 0>; + }; + + alt10_ta5_sl: alt101 { + alts = <&scfg 0x10 0x1 0>; + }; + + alt10_tb4_sl: alt102 { + alts = <&scfg 0x10 0x2 0>; + }; + + alt10_ta4_sl: alt103 { + alts = <&scfg 0x10 0x3 0>; + }; + + alt10_tb3_2_sl: alt104 { + alts = <&scfg 0x10 0x4 0>; + }; + + alt10_ta3_2_sl: alt105 { + alts = <&scfg 0x10 0x5 0>; + }; + + alt10_tb2_2_sl: alt106 { + alts = <&scfg 0x10 0x6 0>; + }; + + alt10_ta2_2_sl: alt107 { + alts = <&scfg 0x10 0x7 0>; + }; + + /* SCFG DEVALT 11 */ + alt11_adc8_sl: alt110 { + alts = <&scfg 0x11 0x0 0>; + }; + + alt11_adc9_sl: alt111 { + alts = <&scfg 0x11 0x1 0>; + }; + + alt11_adc10_sl: alt112 { + alts = <&scfg 0x11 0x2 0>; + }; + + alt11_adc11_sl: alt113 { + alts = <&scfg 0x11 0x3 0>; + }; + + /* SCFG DEVALT 12 */ + smb1a_pu_sl: alt120 { + alts = <&scfg 0x12 0x0 0>; + }; + + smb1b_pu_sl: alt121 { + alts = <&scfg 0x12 0x1 0>; + }; + + smb2a_pu_sl: alt122 { + alts = <&scfg 0x12 0x2 0>; + }; + + smb2b_pu_sl: alt123 { + alts = <&scfg 0x12 0x3 0>; + }; + + smb3a_pu_sl: alt124 { + alts = <&scfg 0x12 0x4 0>; + }; + + smb3b_pu_sl: alt125 { + alts = <&scfg 0x12 0x5 0>; + }; + + smb4a_pu_sl: alt126 { + alts = <&scfg 0x12 0x6 0>; + }; + + smb4b_pu_sl: alt127 { + alts = <&scfg 0x12 0x7 0>; + }; + + /* SCFG DEVALT CX */ + altcx_psl_in0_ahi: alt131 { + alts = <&scfg 0x13 0x1 0>; + }; + + altcx_psl_in1_ahi: alt132 { + alts = <&scfg 0x13 0x2 0>; + }; + + altcx_psl_in2_ahi: alt133 { + alts = <&scfg 0x13 0x3 0>; + }; + + altcx_psl_in3_ahi: alt134 { + alts = <&scfg 0x13 0x4 0>; + }; + + altcx_psl_in4_ahi: alt135 { + alts = <&scfg 0x13 0x5 0>; + }; + + altcx_psl_in5_ahi: alt136 { + alts = <&scfg 0x13 0x6 0>; + }; + + altcx_gpio_out_pullen: alt137 { + alts = <&scfg 0x13 0x7 0>; + }; + + /* SCFG DEVALT DX */ + altdx_psl_out_gpo: alt140 { + alts = <&scfg 0x14 0x0 0>; + }; + + altdx_psl_fw_ctl_high: alt141 { + alts = <&scfg 0x14 0x1 0>; + }; + + altdx_psl_fw_ctl_low: alt141-inv { + alts = <&scfg 0x14 0x1 1>; + }; + + altdx_gpstby_rst_bit: alt147 { + alts = <&scfg 0x14 0x7 0>; + }; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck-espi-vws-map.dtsi b/dts/arm/nuvoton/npck/npck-espi-vws-map.dtsi new file mode 100644 index 00000000000..3a9b8aadb6e --- /dev/null +++ b/dts/arm/nuvoton/npck/npck-espi-vws-map.dtsi @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* + * Nuvoton NPCK3 eSPI Virtual Wires Mapping Table + * |--------------------------------------------------------------------------| + * | VW idx | SLV reg | Wire Bit 3 | Wire Bit 2 | Wire Bit 1| Wire Bit 0 | + * |--------------------------------------------------------------------------| + * | Input (Master-to-Slave) Virtual Wires | + * |--------------------------------------------------------------------------| + * | 02h[S] | VWEVMS0 | Reserved | SLP_S5# | SLP_S4# | SLP_S3# | + * | 03h[S] | VWEVMS1 | Reserved | OOB_RST_WARN | PLTRST# | SUS_STAT# | + * | 07h[S] | VWEVMS2 | Reserved | Reserved | Reserved | HOS_RST_WARN| + * | 41h[P] | VWEVMS3 | SLP_A# | Reserved | SUS_PDNACK| SUS_WARN# | + * | 42h[P] | VWEVMS4 | Reserved | Reserved | SLP_WLAN# | SLP_LAN# | + * |--------------------------------------------------------------------------| + * | Output (Slave-to-Master) Virtual Wires | + * |--------------------------------------------------------------------------| + * | 04h[S] | VWEVSM0 | PME# | WAKE# | Reserved | OOB_RST_ACK | + * | 05h[S] | VWEVSM1 | SLV_BOOT_STS | ERR_NONFATAL | ERR_FATAL | SLV_BT_DONE | + * | 06h[S] | VWEVSM2 | HOST_RST_ACK | Reserved | SMI# | SCI# | + * | 40h[P] | VWEVSM3 | Reserved | Reserved | Reserved | SUS_ACK# | + * |--------------------------------------------------------------------------| + * [S] System-/[P] Platform-Specific Virtual Wires + */ + +/ { + npcx-espi-vws-map { + compatible = "nuvoton,npcx-espi-vw-conf"; + + /* eSPI Virtual Vire (VW) input configuration */ + /* index 02h (In) */ + vw-slp-s3 { + vw-reg = ; + vw-wui = <&wui_vw_slp_s3>; + }; + + vw-slp-s4 { + vw-reg = ; + vw-wui = <&wui_vw_slp_s4>; + }; + + vw-slp-s5 { + vw-reg = ; + vw-wui = <&wui_vw_slp_s5>; + }; + + /* index 03h (In) */ + vw-sus-stat { + vw-reg = ; + vw-wui = <&wui_vw_sus_stat>; + }; + + vw-plt-rst { + vw-reg = ; + vw-wui = <&wui_vw_plt_rst>; + }; + + vw-oob-rst-warn { + vw-reg = ; + vw-wui = <&wui_vw_oob_rst_warn>; + }; + + /* index 07h (In) */ + vw-host-rst-warn { + vw-reg = ; + vw-wui = <&wui_vw_host_rst_warn>; + }; + + /* index 41h (In) */ + vw-sus-warn { + vw-reg = ; + vw-wui = <&wui_vw_sus_warn>; + }; + + vw-sus-pwrdn-ack { + vw-reg = ; + vw-wui = <&wui_vw_sus_pwrdn_ack>; + }; + + vw-slp-a { + vw-reg = ; + vw-wui = <&wui_vw_slp_a>; + }; + + /* index 42h (In) */ + vw-slp-lan { + vw-reg = ; + vw-wui = <&wui_vw_slp_lan>; + }; + + vw-slp-wlan { + vw-reg = ; + vw-wui = <&wui_vw_slp_wlan>; + }; + + /* eSPI Virtual Vire (VW) output configuration */ + /* index 04h (Out) */ + vw-oob-rst-ack { + vw-reg = ; + }; + + vw-wake { + vw-reg = ; + }; + + vw-pme { + vw-reg = ; + }; + + /* index 05h (Out) */ + vw-slv-boot-done { + vw-reg = ; + }; + + vw-err-fatal { + vw-reg = ; + }; + + vw-err-non-fatal { + vw-reg = ; + }; + + vw-slv-boot-sts-with-done { + /* + * SLAVE_BOOT_DONE & SLAVE_LOAD_STS bits (bit 0 & bit 3) + * have to be sent together. Hence its bitmask is 0x09. + */ + vw-reg = ; + }; + + /* index 06h (Out) */ + vw-sci { + vw-reg = ; + }; + + vw-smi { + vw-reg = ; + }; + + vw-host-rst-ack { + vw-reg = ; + }; + + /* index 40h (Out) */ + vw-sus-ack { + vw-reg = ; + }; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck-lvol-ctrl-map.dtsi b/dts/arm/nuvoton/npck/npck-lvol-ctrl-map.dtsi new file mode 100644 index 00000000000..23c632f6e8b --- /dev/null +++ b/dts/arm/nuvoton/npck/npck-lvol-ctrl-map.dtsi @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + def-lvol-conf-list { + compatible = "nuvoton,npcx-lvolctrl-conf"; + + /* Low-Voltage IO Control 0 */ + lvol_io20: lvol00 { + lvols = <&scfg 0 0>; + }; + + lvol_io21: lvol01 { + lvols = <&scfg 0 1>; + }; + + lvol_io40: lvol02 { + lvols = <&scfg 0 2>; + }; + + lvol_io54: lvol03 { + lvols = <&scfg 0 3>; + }; + + lvol_io85: lvol05 { + lvols = <&scfg 0 5>; + }; + + lvol_io86: lvol06 { + lvols = <&scfg 0 6>; + }; + + lvol_io94: lvol07 { + lvols = <&scfg 0 7>; + }; + + /* Low-Voltage IO Control 1 */ + lvol_iod5: lvol10 { + lvols = <&scfg 1 0>; + }; + + lvol_iod6: lvol11 { + lvols = <&scfg 1 1>; + }; + + lvol_io46: lvol12 { + lvols = <&scfg 1 2>; + }; + + lvol_io44: lvol13 { + lvols = <&scfg 1 3>; + }; + + lvol_io50: lvol14 { + lvols = <&scfg 1 4>; + }; + + lvol_io52: lvol15 { + lvols = <&scfg 1 5>; + }; + + lvol_ioe1: lvol16 { + lvols = <&scfg 1 6>; + }; + + lvol_ioe2: lvol17 { + lvols = <&scfg 1 7>; + }; + + /* Low-Voltage IO Control 2 */ + lvol_io01: lvol20 { + lvols = <&scfg 2 0>; + }; + + lvol_io03: lvol21 { + lvols = <&scfg 2 1>; + }; + + lvol_io13: lvol22 { + lvols = <&scfg 2 2>; + }; + + lvol_io15: lvol23 { + lvols = <&scfg 2 3>; + }; + + lvol_io45: lvol24 { + lvols = <&scfg 2 4>; + }; + + lvol_io51: lvol25 { + lvols = <&scfg 2 5>; + }; + + lvol_ioe3: lvol26 { + lvols = <&scfg 2 6>; + }; + + lvol_ioe4: lvol27 { + lvols = <&scfg 2 7>; + }; + + /* Low-Voltage IO Control 3 */ + lvol_io22: lvol30 { + lvols = <&scfg 3 0>; + }; + + lvol_io17: lvol31 { + lvols = <&scfg 3 1>; + }; + + lvol_io74: lvol32 { + lvols = <&scfg 3 2>; + }; + + lvol_io73: lvol33 { + lvols = <&scfg 3 3>; + }; + + lvol_io31: lvol34 { + lvols = <&scfg 3 4>; + }; + + lvol_io23: lvol35 { + lvols = <&scfg 3 5>; + }; + + lvol_io53: lvol36 { + lvols = <&scfg 3 6>; + }; + + lvol_io47: lvol37 { + lvols = <&scfg 3 7>; + }; + + /* Low-Voltage IO Control 4 */ + lvol_io25: lvol40 { + lvols = <&scfg 4 0>; + }; + + lvol_ioe6: lvol41 { + lvols = <&scfg 4 1>; + }; + + lvol_ioc0: lvol42 { + lvols = <&scfg 4 2>; + }; + + lvol_iob7: lvol43 { + lvols = <&scfg 4 3>; + }; + + /* + * Pseudo Low-Voltage IO Control (i.e. IO pad doesn't support + * low voltage detection.) + */ + lvol_none: lvol-pseudo { + lvols = <&scfg 31 0>; + }; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck-miwus-int-map.dtsi b/dts/arm/nuvoton/npck/npck-miwus-int-map.dtsi new file mode 100644 index 00000000000..e1232a99eed --- /dev/null +++ b/dts/arm/nuvoton/npck/npck-miwus-int-map.dtsi @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* Mapping between MIWU group and interrupts */ + npcx-miwus-int-map { + map_miwu0_groups: map-miwu0-groups { + compatible = "nuvoton,npcx-miwu-int-map"; + parent = <&miwu0>; + + group_a0: group-a0-map { + irq = <40>; + irq-prio = <2>; + group-mask = <0x01>; + }; + + group_b0: group-b0-map { + irq = <41>; + irq-prio = <2>; + group-mask = <0x02>; + }; + + group_c0: group-c0-map { + irq = <42>; + irq-prio = <2>; + group-mask = <0x04>; + }; + + group_d0: group-d0-map { + irq = <43>; + irq-prio = <2>; + group-mask = <0x08>; + }; + + group_e0: group-e0-map { + irq = <44>; + irq-prio = <2>; + group-mask = <0x10>; + }; + + group_f0: group-f0-map { + irq = <45>; + irq-prio = <2>; + group-mask = <0x20>; + }; + + group_g0: group-g0-map { + irq = <46>; + irq-prio = <2>; + group-mask = <0x40>; + }; + + group_h0: group-h0-map { + irq = <47>; + irq-prio = <2>; + group-mask = <0x80>; + }; + }; + + map_miwu1_groups: map-miwu1-groups { + compatible = "nuvoton,npcx-miwu-int-map"; + parent = <&miwu1>; + + group_a1: group-a1-map { + irq = <48>; + irq-prio = <2>; + group-mask = <0x01>; + }; + + group_b1: group-b1-map { + irq = <49>; + irq-prio = <2>; + group-mask = <0x02>; + }; + + group_c1: group-c1-map { + irq = <50>; + irq-prio = <2>; + group-mask = <0x04>; + }; + + group_d1: group-d1-map { + irq = <51>; + irq-prio = <2>; + group-mask = <0x08>; + }; + + group_e1: group-e1-map { + irq = <12>; + irq-prio = <2>; + group-mask = <0x10>; + }; + + group_f1: group-f1-map { + irq = <53>; + irq-prio = <2>; + group-mask = <0x20>; + }; + + group_g1: group-g1-map { + irq = <54>; + irq-prio = <2>; + group-mask = <0x40>; + }; + + group_h1: group-h1-map { + irq = <55>; + irq-prio = <2>; + group-mask = <0x80>; + }; + }; + + map_miwu2_groups: map-miwu2-groups { + compatible = "nuvoton,npcx-miwu-int-map"; + parent = <&miwu2>; + + group_a2: group-a2-map { + irq = <60>; + irq-prio = <2>; + group-mask = <0x01>; + }; + + group_b2: group-b2-map { + irq = <61>; + irq-prio = <2>; + group-mask = <0x02>; + }; + + group_c2: group-c2-map { + irq = <62>; + irq-prio = <2>; + group-mask = <0x04>; + }; + + group_d2: group-d2-map { + irq = <63>; + irq-prio = <2>; + group-mask = <0x08>; + }; + + group_e2: group-e2-map { + irq = <56>; + irq-prio = <2>; + group-mask = <0x10>; + }; + + group_f2: group-f2-map { + irq = <57>; + irq-prio = <2>; + group-mask = <0x20>; + }; + + group_g2: group-g2-map { + irq = <58>; + irq-prio = <2>; + group-mask = <0x40>; + }; + + group_h2: group-h2-map { + irq = <59>; + irq-prio = <2>; + group-mask = <0x80>; + }; + }; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi b/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi new file mode 100644 index 00000000000..d155b9ff749 --- /dev/null +++ b/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi @@ -0,0 +1,608 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* Mapping between MIWU wui bits and source device */ + npcx-miwus-wui-map { + compatible = "nuvoton,npcx-miwu-wui-map"; + + /* MIWU table 0 */ + /* MIWU group A */ + wui_io01: wui0-1-1 { + miwus = <&miwu0 0 1>; /* GPIO01 */ + }; + + wui_io02: wui0-1-2 { + miwus = <&miwu0 0 2>; /* GPIO02 */ + }; + + wui_io03: wui0-1-3 { + miwus = <&miwu0 0 3>; /* GPIO03 */ + }; + + wui_io04: wui0-1-4 { + miwus = <&miwu0 0 4>; /* GPIO04 */ + }; + + wui_io05: wui0-1-5 { + miwus = <&miwu0 0 5>; /* GPIO05 */ + }; + + wui_io07: wui0-1-7 { + miwus = <&miwu0 0 7>; /* GPIO07 */ + }; + + /* MIWU group B */ + wui_io10: wui0-2-0 { + miwus = <&miwu0 1 0>; /* GPIO10 */ + }; + + wui_io11: wui0-2-1 { + miwus = <&miwu0 1 1>; /* GPIO11 */ + }; + + wui_io13: wui0-2-3 { + miwus = <&miwu0 1 3>; /* GPIO13 */ + }; + + wui_io14: wui0-2-4 { + miwus = <&miwu0 1 4>; /* GPIO14 */ + }; + + wui_io15: wui0-2-5 { + miwus = <&miwu0 1 5>; /* GPIO15 */ + }; + + wui_io17: wui0-2-7 { + miwus = <&miwu0 1 7>; /* GPIO17 */ + }; + + /* MIWU group C */ + wui_io20: wui0-3-0 { + miwus = <&miwu0 2 0>; /* GPIO20 */ + }; + + wui_io21: wui0-3-1 { + miwus = <&miwu0 2 1>; /* GPIO21 */ + }; + + wui_io22: wui0-3-2 { + miwus = <&miwu0 2 2>; /* GPIO22 */ + }; + + wui_io23: wui0-3-3 { + miwus = <&miwu0 2 3>; /* GPIO23 */ + }; + + wui_io25: wui0-3-5 { + miwus = <&miwu0 2 5>; /* GPIO25 */ + }; + + wui_io26: wui0-3-6 { + miwus = <&miwu0 2 6>; /* GPIO26 */ + }; + + wui_io27: wui0-3-7 { + miwus = <&miwu0 2 7>; /* GPIO27 */ + }; + + /* MIWU group D */ + wui_io30: wui0-4-0 { + miwus = <&miwu0 3 0>; /* GPIO30 */ + }; + + wui_io31: wui0-4-1 { + miwus = <&miwu0 3 1>; /* GPIO31 */ + }; + + wui_io32: wui0-4-2 { + miwus = <&miwu0 3 2>; /* GPIO32 */ + }; + + wui_io33: wui0-4-3 { + miwus = <&miwu0 3 3>; /* GPIO33 */ + }; + + wui_io34: wui0-4-4 { + miwus = <&miwu0 3 4>; /* GPIO34 */ + }; + + wui_io36: wui0-4-6 { + miwus = <&miwu0 3 6>; /* GPIO36 */ + }; + + /* MIWU group E */ + wui_io40: wui0-5-0 { + miwus = <&miwu0 4 0>; /* GPIO40 */ + }; + + wui_io44: wui0-5-4 { + miwus = <&miwu0 4 4>; /* GPIO44 */ + }; + + wui_io45: wui0-5-5 { + miwus = <&miwu0 4 5>; /* GPIO45 */ + }; + + wui_io46: wui0-5-6 { + miwus = <&miwu0 4 6>; /* GPIO46 */ + }; + + wui_io47: wui0-5-7 { + miwus = <&miwu0 4 7>; /* GPIO47 */ + }; + + /* MIWU group F */ + wui_io50: wui0-6-0 { + miwus = <&miwu0 5 0>; /* GPIO50 */ + }; + + wui_io51: wui0-6-1 { + miwus = <&miwu0 5 1>; /* GPIO51 */ + }; + + wui_io52: wui0-6-2 { + miwus = <&miwu0 5 2>; /* GPIO52 */ + }; + + wui_io53: wui0-6-3 { + miwus = <&miwu0 5 3>; /* GPIO53 */ + }; + + wui_io54: wui0-6-4 { + miwus = <&miwu0 5 4>; /* GPIO54 */ + }; + + wui_io55: wui0-6-5 { + miwus = <&miwu0 5 5>; /* GPIO55 */ + }; + + wui_io56: wui0-6-6 { + miwus = <&miwu0 5 6>; /* GPIO56 */ + }; + + wui_io57: wui0-6-7 { + miwus = <&miwu0 5 7>; /* GPIO57 */ + }; + + /* MIWU group G */ + wui_io60: wui0-7-0 { + miwus = <&miwu0 6 0>; /* GPIO60 */ + }; + + wui_io61: wui0-7-1 { + miwus = <&miwu0 6 1>; /* GPIO61 */ + }; + + wui_io62: wui0-7-2 { + miwus = <&miwu0 6 2>; /* GPIO62 */ + }; + + wui_io63: wui0-7-3 { + miwus = <&miwu0 6 3>; /* GPIO63 */ + }; + + wui_io64: wui0-7-4 { + miwus = <&miwu0 6 4>; /* GPIO64 */ + }; + + wui_io65: wui0-7-5 { + miwus = <&miwu0 6 5>; /* GPIO65 */ + }; + + wui_io66: wui0-7-6 { + miwus = <&miwu0 6 6>; /* GPIO66 */ + }; + + wui_io67: wui0-7-7 { + miwus = <&miwu0 6 7>; /* GPIO67 */ + }; + + /* MIWU group H */ + wui_io70: wui0-8-0 { + miwus = <&miwu0 7 0>; /* GPIO70 */ + }; + + wui_io72: wui0-8-2 { + miwus = <&miwu0 7 2>; /* GPIO72 */ + }; + + wui_io73: wui0-8-3 { + miwus = <&miwu0 7 3>; /* GPIO73 */ + }; + + wui_io74: wui0-8-4 { + miwus = <&miwu0 7 4>; /* GPIO74 */ + }; + + wui_io75: wui0-8-5 { + miwus = <&miwu0 7 5>; /* GPIO75 */ + }; + + wui_io76: wui0-8-6 { + miwus = <&miwu0 7 6>; /* GPIO76 */ + }; + + wui_io77: wui0-8-7 { + miwus = <&miwu0 7 7>; /* GPIO77 */ + }; + + /* MIWU table 1 */ + /* MIWU group A */ + wui_io81: wui1-1-1 { + miwus = <&miwu1 0 1>; /* GPIO81 */ + }; + + wui_io83: wui1-1-3 { + miwus = <&miwu1 0 3>; /* GPIO83 */ + }; + + wui_io85: wui1-1-5 { + miwus = <&miwu1 0 5>; /* GPIO85 */ + }; + + wui_io86: wui1-1-6 { + miwus = <&miwu1 0 6>; /* GPIO86 */ + }; + + wui_io87: wui1-1-7 { + miwus = <&miwu1 0 7>; /* GPIO87 */ + }; + + wui_cr_sin1: wui1-1-7-1 { + miwus = <&miwu1 0 7>; /* CR_SIN */ + }; + + /* MIWU group B */ + wui_io90: wui1-2-0 { + miwus = <&miwu1 1 0>; /* GPIO90 */ + }; + + wui_io91: wui1-2-1 { + miwus = <&miwu1 1 1>; /* GPIO91 */ + }; + + wui_io92: wui1-2-2 { + miwus = <&miwu1 1 2>; /* GPIO92 */ + }; + + wui_io93: wui1-2-3 { + miwus = <&miwu1 1 3>; /* GPIO93 */ + }; + + wui_io94: wui1-2-4 { + miwus = <&miwu1 1 4>; /* GPIO94 */ + }; + + /* MIWU group C */ + wui_ioa0: wui1-3-0 { + miwus = <&miwu1 2 0>; /* GPIOA0 */ + }; + + wui_ioa1: wui1-3-1 { + miwus = <&miwu1 2 1>; /* GPIOA1 */ + }; + + wui_ioa2: wui1-3-2 { + miwus = <&miwu1 2 2>; /* GPIOA2 */ + }; + + wui_ioa3: wui1-3-3 { + miwus = <&miwu1 2 3>; /* GPIOA3 */ + }; + + wui_ioa4: wui1-3-4 { + miwus = <&miwu1 2 4>; /* GPIOA4 */ + }; + + wui_ioa5: wui1-3-5 { + miwus = <&miwu1 2 5>; /* GPIOA5 */ + }; + + wui_ioa6: wui1-3-6 { + miwus = <&miwu1 2 6>; /* GPIOA6 */ + }; + + wui_ioa7: wui1-3-7 { + miwus = <&miwu1 2 7>; /* GPIOA7 */ + }; + + /* MIWU group D */ + wui_iob0: wui1-4-0 { + miwus = <&miwu1 3 0>; /* GPIOB0 */ + }; + + wui_shi_cs: wui1-4-3 { + miwus = <&miwu1 3 3>; /* SHI_CS */ + }; + + wui_cdbgpwrupreq: wui1-4-4 { + miwus = <&miwu1 3 4>; /* CDBGPWRUPREQ */ + }; + + wui_lpc_ev_wkup: wui1-4-5 { + miwus = <&miwu1 3 5>; /* LPC_EV_WKUP */ + }; + + wui_host_acc: wui1-4-6 { + miwus = <&miwu1 3 6>; /* HOST_ACC */ + }; + + wui_espi_rst: wui1-4-7 { + miwus = <&miwu1 3 7>; /* ESPI_RST */ + }; + + /* MIWU group E */ + wui_mswc: wui1-5-2 { + miwus = <&miwu1 4 2>; /* MSWC */ + }; + + wui_t0out: wui1-5-3 { + miwus = <&miwu1 4 3>; /* T0OUT */ + }; + + /* MIWU group F */ + wui_iod0: wui1-6-0 { + miwus = <&miwu1 5 0>; /* GPIOD0 */ + }; + + wui_iod3: wui1-6-3 { + miwus = <&miwu1 5 3>; /* GPIOD3 */ + }; + + wui_iod4: wui1-6-4 { + miwus = <&miwu1 5 4>; /* GPIOD4 */ + }; + + wui_iod5: wui1-6-5 { + miwus = <&miwu1 5 5>; /* GPIOD5 */ + }; + + wui_iod6: wui1-6-6 { + miwus = <&miwu1 5 6>; /* GPIOD6 */ + }; + + wui_iod7: wui1-6-7 { + miwus = <&miwu1 5 7>; /* GPIOD7 */ + }; + + /* MIWU group G */ + wui_ioe0: wui1-7-0 { + miwus = <&miwu1 6 0>; /* GPIOE0 */ + }; + + wui_ioe1: wui1-7-1 { + miwus = <&miwu1 6 1>; /* GPIOE1 */ + }; + + wui_ioe2: wui1-7-2 { + miwus = <&miwu1 6 2>; /* GPIOE2 */ + }; + + wui_ioe3: wui1-7-3 { + miwus = <&miwu1 6 3>; /* GPIOE3 */ + }; + + wui_ioe4: wui1-7-4 { + miwus = <&miwu1 6 4>; /* GPIOE4 */ + }; + + wui_ioe5: wui1-7-5 { + miwus = <&miwu1 6 5>; /* GPIOE5 */ + }; + + wui_ioe6: wui1-7-6 { + miwus = <&miwu1 6 6>; /* GPIOE6 */ + }; + + /* MIWU group H */ + wui_mtc: wui1-8-0 { + miwus = <&miwu1 7 0>; /* MTC */ + }; + + wui_smb1: wui1-8-1 { + miwus = <&miwu1 7 1>; /* SMB1 */ + }; + + wui_smb2: wui1-8-2 { + miwus = <&miwu1 7 2>; /* SMB2 */ + }; + + wui_smb3: wui1-8-3 { + miwus = <&miwu1 7 3>; /* SMB3 */ + }; + + wui_smb4: wui1-8-4 { + miwus = <&miwu1 7 4>; /* SMB4 */ + }; + + wui_smb5: wui1-8-5 { + miwus = <&miwu1 7 5>; /* SMB5 */ + }; + + wui_smb6: wui1-8-6 { + miwus = <&miwu1 7 6>; /* SMB6 */ + }; + + /* MIWU table 2 */ + /* MIWU group A */ + wui_vw_slp_s3: wui2-1-0 { + miwus = <&miwu2 0 0>; /* SLP_S3_L */ + }; + + wui_vw_slp_s4: wui2-1-1 { + miwus = <&miwu2 0 1>; /* SLP_S4_L */ + }; + + wui_vw_slp_s5: wui2-1-2 { + miwus = <&miwu2 0 2>; /* SLP_S5_L */ + }; + + wui_vw_sus_stat: wui2-1-4 { + miwus = <&miwu2 0 4>; /* SUS_STAT_L */ + }; + + wui_vw_plt_rst: wui2-1-5 { + miwus = <&miwu2 0 5>; /* PLTRST_L */ + }; + + wui_vw_oob_rst_warn: wui2-1-6 { + miwus = <&miwu2 0 6>; /* OOB_RST_WARN */ + }; + + /* MIWU group B */ + wui_vw_host_rst_warn: wui2-2-0 { + miwus = <&miwu2 1 0>; /* HOST_RST_WARN */ + }; + + wui_vw_sus_warn: wui2-2-4 { + miwus = <&miwu2 1 4>; /* SUS_WARN_L */ + }; + + wui_vw_sus_pwrdn_ack: wui2-2-5 { + miwus = <&miwu2 1 5>; /* SUS_PWRDN_ACK */ + }; + + wui_vw_slp_a: wui2-2-7 { + miwus = <&miwu2 1 7>; /* SLP_A_L */ + }; + + /* MIWU group C */ + wui_vw_slp_lan: wui2-3-0 { + miwus = <&miwu2 2 0>; /* SLP_LAN_L */ + }; + + wui_vw_slp_wlan: wui2-3-1 { + miwus = <&miwu2 2 1>; /* SLP_WLAN_L */ + }; + + wui_vw_pch_to_ec_gen_0: wui2-3-4 { + miwus = <&miwu2 2 4>; /* PCH_TO_EC_GENERIC_0 */ + }; + + wui_vw_pch_to_ec_gen_1: wui2-3-5 { + miwus = <&miwu2 2 5>; /* PCH_TO_EC_GENERIC_1 */ + }; + + wui_vw_pch_to_ec_gen_2: wui2-3-6 { + miwus = <&miwu2 2 6>; /* PCH_TO_EC_GENERIC_2 */ + }; + + wui_vw_pch_to_ec_gen_3: wui2-3-7 { + miwus = <&miwu2 2 7>; /* PCH_TO_EC_GENERIC_3 */ + }; + + /* MIWU group D */ + wui_vw_pch_to_ec_gen_4: wui2-4-0 { + miwus = <&miwu2 3 0>; /* PCH_TO_EC_GENERIC_4 */ + }; + + wui_vw_pch_to_ec_gen_5: wui2-4-1 { + miwus = <&miwu2 3 1>; /* PCH_TO_EC_GENERIC_5 */ + }; + + wui_vw_pch_to_ec_gen_6: wui2-4-2 { + miwus = <&miwu2 3 2>; /* PCH_TO_EC_GENERIC_6 */ + }; + + wui_vw_pch_to_ec_gen_7: wui2-4-3 { + miwus = <&miwu2 3 3>; /* PCH_TO_EC_GENERIC_7 */ + }; + + wui_vw_host_c10: wui2-4-4 { + miwus = <&miwu2 3 4>; /* HOST_C10 */ + }; + + /* MIWU group E */ + wui_iog5: wui2-5-5 { + miwus = <&miwu2 4 5>; /* GPIOG5 */ + }; + + wui_iog6: wui2-5-6 { + miwus = <&miwu2 4 6>; /* GPIOG6 */ + }; + + wui_iog7: wui2-5-7 { + miwus = <&miwu2 4 7>; /* GPIOG7 */ + }; + + /* MIWU group F */ + wui_ioh0: wui2-6-0 { + miwus = <&miwu2 5 0>; /* GPIOH0 */ + }; + + wui_ioh1: wui2-6-1 { + miwus = <&miwu2 5 1>; /* GPIOH1 */ + }; + + wui_ioh2: wui2-6-2 { + miwus = <&miwu2 5 2>; /* GPIOH2 */ + }; + + wui_ioh4: wui2-6-4 { + miwus = <&miwu2 5 4>; /* GPIOH4 */ + }; + + /* MIWU group G */ + wui_io_stb00: wui2-7-0 { + miwus = <&miwu2 6 0>; /* GPIO_STB00 */ + }; + + wui_io_stb01: wui2-7-1 { + miwus = <&miwu2 6 1>; /* GPIO_STB01 */ + }; + + wui_io_stb02: wui2-7-2 { + miwus = <&miwu2 6 2>; /* GPIO_STB02 */ + }; + + wui_io_stb03: wui2-7-3 { + miwus = <&miwu2 6 3>; /* GPIO_STB03 */ + }; + + wui_io_stb04: wui2-7-4 { + miwus = <&miwu2 6 4>; /* GPIO_STB04 */ + }; + + /* MIWU group H */ + wui_io_stb11_psl_in0: wui2-8-1 { + miwus = <&miwu2 7 1>; /* GPIO_STB11/PSL_IN0 */ + }; + + wui_io_stb12_psl_in1: wui2-8-2 { + miwus = <&miwu2 7 2>; /* GPIO_STB12/PSL_IN1 */ + }; + + wui_io_stb13_psl_in2: wui2-8-3 { + miwus = <&miwu2 7 3>; /* GPIO_STB13/PSL_IN2 */ + }; + + wui_io_stb14_psl_in3: wui2-8-4 { + miwus = <&miwu2 7 4>; /* GPIO_STB14/PSL_IN3 */ + }; + + wui_io_stb15_psl_in4: wui2-8-5 { + miwus = <&miwu2 7 5>; /* GPIO_STB15/PSL_IN4 */ + }; + + wui_io_stb16_psl_in5: wui2-8-6 { + miwus = <&miwu2 7 6>; /* GPIO_STB16/PSL_IN5 */ + }; + + /* Pseudo wui item means no mapping between source and wui */ + wui_none: wui-pseudo { + miwus = <&miwu_none 7 7>; + }; + }; + + /* Pseudo MIWU device to present no mapping relationship */ + miwu_none: miwu-pseudo { + compatible = "nuvoton,npcx-miwu"; + index = <3>; + #miwu-cells = <2>; + status = "disabled"; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck.dtsi b/dts/arm/nuvoton/npck/npck.dtsi new file mode 100644 index 00000000000..b8d49194d58 --- /dev/null +++ b/dts/arm/nuvoton/npck/npck.dtsi @@ -0,0 +1,693 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Macros for device tree declarations of npcx soc family */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + + power-states { + suspend_to_idle0: suspend-to-idle0 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <0>; + min-residency-us = <1000>; + }; + + suspend_to_idle1: suspend-to-idle1 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <1>; + min-residency-us = <201000>; + }; + }; + }; + + def-io-conf-list { + compatible = "nuvoton,npcx-pinctrl-def"; + /* Change default functional pads to GPIOs here. */ + pinmux = <>; + }; + + /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. + * Then, the user can override the pin control options at the board level. + */ + pinctrl: pinctrl { + compatible = "nuvoton,npcx-pinctrl"; + status = "okay"; + }; + + /* Dummy node of IOs that have leakage current. The user can override + * 'leak-gpios' prop. at board DT file to save more power consumption. + */ + power_leakage_io: power-leakage-io { + compatible = "nuvoton,npcx-leakage-io"; + status = "okay"; + }; + + soc { + bbram: bb-ram@400af000 { + compatible = "nuvoton,npcx-bbram"; + reg = <0x400af000 0x100 + 0x400af100 0x1>; + reg-names = "memory", "status"; + }; + + pcc: clock-controller@4000d000 { + compatible = "nuvoton,npcx-pcc"; + /* Cells for bus type, clock control reg and bit */ + #clock-cells = <3>; + /* First reg region is Power Management Controller */ + /* Second reg region is Core Domain Clock Generator */ + reg = <0x4000d000 0x2000 + 0x400b5000 0x2000>; + reg-names = "pmc", "cdcg"; + }; + + scfg: scfg@400c3000 { + compatible = "nuvoton,npcx-scfg"; + /* First reg region is System Configuration Device */ + /* Second reg region is Debugger Interface Device */ + /* Third reg region is System Glue Device */ + reg = <0x400c3000 0x70 + 0x400c3070 0x30 + 0x400a5000 0x2000>; + reg-names = "scfg", "dbg", "glue"; + #alt-cells = <3>; + #lvol-cells = <2>; + }; + + mdc: mdc@4000c000 { + compatible = "syscon"; + reg = <0x4000c000 0xa>; + reg-io-width = <1>; + }; + + mdc_header: mdc@4000c00a { + compatible = "syscon"; + reg = <0x4000c00a 0x4>; + reg-io-width = <2>; + }; + + miwu0: miwu@400bb000 { + compatible = "nuvoton,npcx-miwu"; + reg = <0x400bb000 0x2000>; + index = <0>; + #miwu-cells = <2>; + }; + + miwu1: miwu@400bd000 { + compatible = "nuvoton,npcx-miwu"; + reg = <0x400bd000 0x2000>; + index = <1>; + #miwu-cells = <2>; + }; + + miwu2: miwu@400bf000 { + compatible = "nuvoton,npcx-miwu"; + reg = <0x400bf000 0x2000>; + index = <2>; + #miwu-cells = <2>; + }; + + gpio0: gpio@40081000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40081000 0x2000>; + gpio-controller; + index = <0x0>; + #gpio-cells = <2>; + }; + + gpio1: gpio@40083000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40083000 0x2000>; + gpio-controller; + index = <0x1>; + #gpio-cells = <2>; + }; + + gpio2: gpio@40085000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40085000 0x2000>; + gpio-controller; + index = <0x2>; + #gpio-cells = <2>; + }; + + gpio3: gpio@40087000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40087000 0x2000>; + gpio-controller; + index = <0x3>; + #gpio-cells = <2>; + }; + + gpio4: gpio@40089000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40089000 0x2000>; + gpio-controller; + index = <0x4>; + #gpio-cells = <2>; + }; + + gpio5: gpio@4008b000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4008b000 0x2000>; + gpio-controller; + index = <0x5>; + #gpio-cells = <2>; + }; + + gpio6: gpio@4008d000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4008d000 0x2000>; + gpio-controller; + index = <0x6>; + #gpio-cells = <2>; + }; + + gpio7: gpio@4008f000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4008f000 0x2000>; + gpio-controller; + index = <0x7>; + #gpio-cells = <2>; + }; + + gpio8: gpio@40091000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40091000 0x2000>; + gpio-controller; + index = <0x8>; + #gpio-cells = <2>; + }; + + gpio9: gpio@40093000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40093000 0x2000>; + gpio-controller; + index = <0x9>; + #gpio-cells = <2>; + }; + + gpioa: gpio@40095000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40095000 0x2000>; + gpio-controller; + index = <0xA>; + #gpio-cells = <2>; + }; + + gpiob: gpio@40097000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40097000 0x2000>; + gpio-controller; + index = <0xB>; + #gpio-cells = <2>; + }; + + gpioc: gpio@40099000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x40099000 0x2000>; + gpio-controller; + index = <0xC>; + #gpio-cells = <2>; + }; + + gpiod: gpio@4009b000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4009b000 0x2000>; + gpio-controller; + index = <0xD>; + #gpio-cells = <2>; + }; + + gpioe: gpio@4009d000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4009d000 0x2000>; + gpio-controller; + index = <0xE>; + #gpio-cells = <2>; + }; + + gpiof: gpio@4009f000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x4009f000 0x2000>; + gpio-controller; + index = <0xF>; + #gpio-cells = <2>; + }; + + gpiog: gpio@400a7000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x400a7000 0x2000>; + gpio-controller; + index = <0x10>; + #gpio-cells = <2>; + }; + + gpioh: gpio@400a9000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x400a9000 0x2000>; + gpio-controller; + index = <0x11>; + #gpio-cells = <2>; + }; + + gpiostb0: gpio@400ab000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x400ab000 0x2000>; + gpio-controller; + index = <0x12>; + #gpio-cells = <2>; + }; + + gpiostb1: gpio@400ad000 { + compatible = "nuvoton,npcx-gpio"; + reg = <0x400ad000 0x2000>; + gpio-controller; + index = <0x13>; + #gpio-cells = <2>; + }; + + pwma: pwm@40080000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40080000 0x2000>; + pwm-channel = <0>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmb: pwm@40082000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40082000 0x2000>; + pwm-channel = <1>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmc: pwm@40084000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40084000 0x2000>; + pwm-channel = <2>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmd: pwm@40086000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40086000 0x2000>; + pwm-channel = <3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmf: pwm@4008a000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x4008a000 0x2000>; + pwm-channel = <5>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmi: pwm@40090000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40090000 0x2000>; + pwm-channel = <9>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL0 0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmj: pwm@40092000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40092000 0x2000>; + pwm-channel = <10>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL0 1>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmk: pwm@40094000 { + compatible = "nuvoton,npcx-pwm"; + reg = <0x40094000 0x2000>; + pwm-channel = <11>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL0 2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + adc0: adc@400d1000 { + compatible = "nuvoton,npcx-adc"; + #io-channel-cells = <1>; + reg = <0x400d1000 0x2000>; + interrupts = <21 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; + vref-mv = <3300>; + status = "disabled"; + }; + + twd0: watchdog@400d8000 { + compatible = "nuvoton,npcx-watchdog"; + reg = <0x400d8000 0x2000>; + t0-out = <&wui_t0out>; + }; + + espi0: espi@4000a000 { + compatible = "nuvoton,npcx-espi"; + reg = <0x4000a000 0x2000>; + interrupts = <11 3>; /* Interrupt for eSPI Bus */ + + /* clocks for eSPI modules */ + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; + /* WUI maps for eSPI signals */ + espi-rst-wui = <&wui_espi_rst>; + + #address-cells = <1>; + #size-cells = <0>; + #vw-cells = <3>; + status = "disabled"; + }; + + host_sub: lpc@400c1000 { + compatible = "nuvoton,npcx-host-sub"; + /* host sub-module register address & size */ + reg = <0x400c1000 0x2000 + 0x40010000 0x2000 + 0x4000e000 0x2000 + 0x400c7000 0x2000 + 0x400c9000 0x2000 + 0x400cb000 0x2000 + 0x400a1000 0x2000>; + reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", + "pm_hcmd", "mbi"; + + /* host sub-module IRQ and priority */ + interrupts = <6 3>, /* KBC Input-Buf-Full (IBF) */ + <5 3>, /* KBC Output-Buf-Empty (OBE) */ + <4 3>, /* PMCH Input-Buf-Full (IBF) */ + <3 3>, /* PMCH Output-Buf-Empty (OBE) */ + <10 3>, /* Port80 FIFO Not Empty */ + <7 3>; /* SHM/MBI interrupts */ + + interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", + "pmch_obe", "p80_fifo", "shm_mbi"; + + /* WUI map for accessing host sub-modules */ + host-acc-wui = <&wui_host_acc>; + + /* clocks for host sub-modules */ + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, + <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL5 7>; + }; + + /* I2c Controllers - Do not use them as i2c node directly */ + i2c_ctrl1: i2c@40003000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40003000 0x1000>; + interrupts = <35 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; + smb-wui = <&wui_smb1>; + status = "disabled"; + }; + + i2c_ctrl2: i2c@40004000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40004000 0x1000>; + interrupts = <36 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; + smb-wui = <&wui_smb2>; + status = "disabled"; + }; + + i2c_ctrl3: i2c@40005000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40005000 0x1000>; + interrupts = <37 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 2>; + smb-wui = <&wui_smb3>; + status = "disabled"; + }; + + i2c_ctrl4: i2c@40006000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40006000 0x1000>; + interrupts = <38 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 3>; + smb-wui = <&wui_smb4>; + status = "disabled"; + }; + + i2c_ctrl5: i2c@40007000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40007000 0x1000>; + interrupts = <39 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; + smb-wui = <&wui_smb5>; + status = "disabled"; + }; + + i2c_ctrl6: i2c@40008000 { + compatible = "nuvoton,npcx-i2c-ctrl"; + reg = <0x40008000 0x1000>; + interrupts = <20 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 5>; + smb-wui = <&wui_smb6>; + status = "disabled"; + }; + + tach1: tach@400e1000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e1000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; + status = "disabled"; + }; + + tach2: tach@400e3000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e3000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; + status = "disabled"; + }; + + tach3: tach@400e5000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e5000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 7>; + status = "disabled"; + }; + + tach4: tach@400e7000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e7000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL0 5>; + status = "disabled"; + }; + + tach5: tach@400e9000 { + compatible = "nuvoton,npcx-tach"; + reg = <0x400e9000 0x2000>; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL0 6>; + status = "disabled"; + }; + + ps2_ctrl0: ps2@400b1000 { + compatible = "nuvoton,npcx-ps2-ctrl"; + reg = <0x400b1000 0x1000>; + interrupts = <8 4>; + clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>; + + /* PS2 Channels - Please use them as PS2 node */ + ps2_channel2: io_ps2_channel2 { + compatible = "nuvoton,npcx-ps2-channel"; + channel = <0x01>; + status = "disabled"; + }; + + ps2_channel3: io_ps2_channel3 { + compatible = "nuvoton,npcx-ps2-channel"; + channel = <0x02>; + status = "disabled"; + }; + }; + + /* Dedicated SPI interface to access SPI flashes */ + qspi_fiu0: quadspi@40020000 { + compatible = "nuvoton,npcx-fiu-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40020000 0x1000>; + clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>; + }; + + peci0: peci@400d4000 { + compatible = "nuvoton,npcx-peci"; + reg = <0x400d4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <9 4>; + clocks = <&pcc NPCX_CLOCK_BUS_FMCLK NPCX_PWDWN_CTL4 5>; + status = "disabled"; + }; + + kbd: kscan@400a3000 { + compatible = "nuvoton,npcx-kbd"; + reg = <0x400a3000 0x2000>; + interrupts = <50 4>; + clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>; + wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3 + &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>; + status = "disabled"; + }; + }; + + soc-if { + /* Soc specific peripheral interface phandles which don't contain + * 'reg' prop. Please overwrite 'status' prop. to 'okay' if you + * want to switch the interface from io to specific peripheral. + */ + host_uart: io_host_uart { + compatible = "nuvoton,npcx-host-uart"; + status = "disabled"; + }; + + i2c1_a: io_i2c_ctrl1_porta { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl1>; + status = "disabled"; + }; + + i2c1_b: io_i2c_ctrl1_portb { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl1>; + status = "disabled"; + }; + + i2c2_a: io_i2c_ctrl2_porta { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl2>; + status = "disabled"; + }; + + i2c2_b: io_i2c_ctrl2_portb { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl2>; + status = "disabled"; + }; + + i2c3_a: io_i2c_ctrl3_porta { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl3>; + status = "disabled"; + }; + + i2c3_b: io_i2c_ctrl3_portb { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl3>; + status = "disabled"; + }; + + i2c4_a: io_i2c_ctrl4_porta { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl4>; + status = "disabled"; + }; + + i2c4_b: io_i2c_ctrl4_portb { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl4>; + status = "disabled"; + }; + + i2c5_a: io_i2c_ctrl5_porta { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + port = ; + controller = <&i2c_ctrl5>; + status = "disabled"; + }; + + i2c6_a: io_i2c_ctrl6_porta { + compatible = "nuvoton,npcx-i2c-port"; + #address-cells = <1>; + #size-cells = <0>; + controller = <&i2c_ctrl6>; + port = ; + status = "disabled"; + }; + + power_ctrl_psl: power-ctrl-psl { + compatible = "nuvoton,npcx-power-psl"; + status = "disabled"; + }; + }; + + soc-id { + compatible = "nuvoton,npcx-soc-id"; + family-id = <0x20>; + }; + + booter-variant { + compatible = "nuvoton,npcx-booter-variant"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/nuvoton/npck/npck3.dtsi b/dts/arm/nuvoton/npck/npck3.dtsi new file mode 100644 index 00000000000..ffdfd49534b --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3.dtsi @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* NPCK3 series pinmux mapping table */ +#include "npck3/npck3-alts-map.dtsi" +/* NPCK3 series mapping table between MIWU wui bits and source device */ +#include "npck3/npck3-miwus-wui-map.dtsi" +/* NPCK3 series mapping table between MIWU groups and interrupts */ +#include "npck3/npck3-miwus-int-map.dtsi" +/* NPCK3 series eSPI VW mapping table */ +#include "npck3/npck3-espi-vws-map.dtsi" +/* NPCK3 series low-voltage io controls mapping table */ +#include "npck3/npck3-lvol-ctrl-map.dtsi" + +/* Device tree declarations of npcx soc family */ +#include "npck.dtsi" + +/ { + def-io-conf-list { + pinmux = <&alt1_dpwrok_sl_def + &alt1_vcc_pwrgd_sl_def + &alt1_lpc_espi_def + &alt2_ecsci_sl_def + &alt7_kso12_sl_def + &alt7_kso13_sl_def + &alt7_kso14_sl_def + &alt7_kso15_sl_def + &alt8_kbrst_sl_def + &alt9_no_ksi0_ksi1_ksi2_ksi3_sl + &alt9_no_ksi4_ksi5_sl + &alt9_no_ksi6_ksi7_sl + &alt9_no_kso0_kso1_kso2_kso3_sl + &alt9_no_kso4_kso5_kso6_kso7_sl + &alt9_no_kso8_kso9_sl + &alt9_no_kso10_kso11_sl + &altf_psl_in0_en_def + &altf_psl_in1_en_def>; + }; + + soc { + /* Specific soc devices in npck3 series */ + itims: timer@400b0000 { + compatible = "nuvoton,npcx-itim-timer"; + reg = <0x400b0000 0x2000 + 0x400bc000 0x2000>; + reg-names = "evt_itim", "sys_itim"; + clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 + &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; + interrupts = <29 1>; /* Event timer interrupt */ + }; + + uart1: serial@400c4000 { + compatible = "nuvoton,npcx-uart"; + reg = <0x400C4000 0x2000>; + interrupts = <23 3>; + clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>; + uart-rx = <&wui_cr_sin1>; + status = "disabled"; + }; + + /* Default clock and power settings in npck3 series */ + pcc: clock-controller@4000d000 { + clock-frequency = ; /* OFMCLK runs at 90MHz */ + core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ + apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ + apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ + apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ + ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */ + pwdwn-ctl-val = <0xe7 /* Start with PWDWN_CTL0 */ + 0xfb /* No FIU_PD */ + 0xff + 0x7f /* No GDMA */ + 0xb7 /* No N2JTAG/SMB_DMA */ + 0xfa /* No CCD/PSL */ + 0x7f>; /* No eSPI */ + }; + + /* Wake-up input source mapping for GPIOs in npck3 series */ + gpio0: gpio@40081000 { + wui-maps = <&wui_none &wui_io01 &wui_io02 &wui_io03 + &wui_io04 &wui_io05 &wui_none &wui_io07>; + + lvol-maps = <&lvol_none &lvol_io01 &lvol_none &lvol_io03 + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpio1: gpio@40083000 { + wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_io13 + &wui_io14 &wui_io15 &wui_none &wui_io17>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io13 + &lvol_none &lvol_io15 &lvol_none &lvol_io17>; + }; + + gpio2: gpio@40085000 { + wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23 + &wui_none &wui_io25 &wui_io26 &wui_io27>; + + lvol-maps = <&lvol_io20 &lvol_io21 &lvol_io22 &lvol_io23 + &lvol_none &lvol_io25 &lvol_none &lvol_none>; + }; + + gpio3: gpio@40087000 { + wui-maps = <&wui_io30 &wui_io31 &wui_io32 &wui_io33 + &wui_io34 &wui_none &wui_io36 &wui_none>; + + lvol-maps = <&lvol_none &lvol_io31 &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpio4: gpio@40089000 { + wui-maps = <&wui_io40 &wui_none &wui_none &wui_none + &wui_io44 &wui_io45 &wui_io46 &wui_io47>; + + lvol-maps = <&lvol_io40 &lvol_none &lvol_none &lvol_none + &lvol_io44 &lvol_io45 &lvol_io46 &lvol_io47>; + }; + + gpio5: gpio@4008b000 { + wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53 + &wui_io54 &wui_io55 &wui_io56 &wui_io57>; + + lvol-maps = <&lvol_io50 &lvol_io51 &lvol_io52 &lvol_io53 + &lvol_io54 &lvol_none &lvol_none &lvol_none>; + }; + + gpio6: gpio@4008d000 { + wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63 + &wui_io64 &wui_io65 &wui_io66 &wui_io67>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpio7: gpio@4008f000 { + wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73 + &wui_io74 &wui_io75 &wui_io76 &wui_io77>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io73 + &lvol_io74 &lvol_none &lvol_none &lvol_none>; + }; + + gpio8: gpio@40091000 { + wui-maps = <&wui_none &wui_io81 &wui_none &wui_io83 + &wui_none &wui_io85 &wui_io86 &wui_io87>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_io85 &lvol_io86 &lvol_none>; + }; + + gpio9: gpio@40093000 { + wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93 + &wui_io94 &wui_none &wui_none &wui_none>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_io94 &lvol_none &lvol_none &lvol_none>; + }; + + gpioa: gpio@40095000 { + wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3 + &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpiob: gpio@40097000 { + wui-maps = <&wui_iob0 &wui_none &wui_none &wui_none + &wui_none &wui_none &wui_none &wui_none>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_iob7>; + }; + + gpioc: gpio@40099000 { + wui-maps = <&wui_none &wui_none &wui_none &wui_none + &wui_none &wui_none &wui_none &wui_none>; + + lvol-maps = <&lvol_ioc0 &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpiod: gpio@4009b000 { + wui-maps = <&wui_iod0 &wui_none &wui_none &wui_iod3 + &wui_iod4 &wui_iod5 &wui_iod6 &wui_iod7>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_iod5 &lvol_iod6 &lvol_none>; + }; + + gpioe: gpio@4009d000 { + wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3 + &wui_ioe4 &wui_ioe5 &wui_ioe6 &wui_none>; + + lvol-maps = <&lvol_none &lvol_ioe1 &lvol_ioe2 &lvol_ioe3 + &lvol_ioe4 &lvol_none &lvol_ioe6 &lvol_none>; + }; + + gpiof: gpio@4009f000 { + wui-maps = <&wui_none &wui_none &wui_none &wui_none + &wui_none &wui_none &wui_none &wui_none>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpiog: gpio@400a7000 { + wui-maps = <&wui_none &wui_none &wui_none &wui_none + &wui_none &wui_iog5 &wui_iog6 &wui_iog7>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpioh: gpio@400a9000 { + wui-maps = <&wui_ioh0 &wui_ioh1 &wui_ioh2 &wui_none + &wui_ioh4 &wui_none &wui_none &wui_none>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpiostb0: gpio@400ab000 { + wui-maps = <&wui_io_stb00 &wui_io_stb01 &wui_io_stb02 &wui_io_stb03 + &wui_io_stb04 &wui_none &wui_none &wui_none>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + gpiostb1: gpio@400ad000 { + wui-maps = <&wui_none &wui_io_stb11_psl_in0 + &wui_io_stb12_psl_in1 &wui_io_stb13_psl_in2 + &wui_io_stb14_psl_in3 &wui_io_stb15_psl_in4 + &wui_io_stb16_psl_in5 &wui_none>; + + lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none + &lvol_none &lvol_none &lvol_none &lvol_none>; + }; + + /* ADC0 comparator configuration in npck3 series */ + adc0: adc@400d1000 { + channel-count = <12>; + threshold-count = <6>; + }; + + espi0: espi@4000a000 { + rx-plsize = <64>; + tx-plsize = <64>; + #address-cells = <1>; + #size-cells = <1>; + espi_taf: espitaf@4000a000 { + compatible = "nuvoton,npcx-espi-taf"; + reg = <0x4000a000 0x2000>, + <0x40021000 0x2000>; + reg-names = "saf", "fiu1"; + status = "disabled"; + }; + }; + }; + + soc-id { + chip-id = <0x09>; + revision-reg = <0x0000FFFC 4>; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck3/npck3-alts-map.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-alts-map.dtsi new file mode 100644 index 00000000000..01e4db28f15 --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3/npck3-alts-map.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common pin-mux configurations in npck */ +#include + +/* Specific pin-mux configurations in npck3 series */ +/ { + npcx-alts-map { + compatible = "nuvoton,npcx-pinctrl-conf"; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck3/npck3-espi-vws-map.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-espi-vws-map.dtsi new file mode 100644 index 00000000000..88c65c37d0b --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3/npck3-espi-vws-map.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common eSPI Virtual Wire (VW) mapping configurations in npck */ +#include + +/* Specific eSPI Virtual Wire (VW) mapping configurations in npck3 series */ diff --git a/dts/arm/nuvoton/npck/npck3/npck3-lvol-ctrl-map.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-lvol-ctrl-map.dtsi new file mode 100644 index 00000000000..067876625bf --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3/npck3-lvol-ctrl-map.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common Low-Voltage level configurations in npck */ +#include + +/* Specific Low-Voltage level configurations in npck3 series */ +/ { + def-lvol-conf-list { + compatible = "nuvoton,npcx-lvolctrl-conf"; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi new file mode 100644 index 00000000000..019284e5b1a --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common MIWU group-interrupt mapping configurations in npck */ +#include + +/* Specific MIWU group-interrupt mapping configurations in npck3 series */ +/ { + /* Mapping between MIWU group and interrupts */ + npcx-miwus-int-map { + }; +}; diff --git a/dts/arm/nuvoton/npck/npck3/npck3-miwus-wui-map.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-miwus-wui-map.dtsi new file mode 100644 index 00000000000..1c5cb93df3f --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3/npck3-miwus-wui-map.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common Wake-Up Unit Input (WUI) mapping configurations in npck */ +#include + +/* Specific Wake-Up Unit Input (WUI) mapping configurations in npck3 series */ +/ { + /* Mapping between MIWU wui bits and source device */ + npcx-miwus-wui-map { + compatible = "nuvoton,npcx-miwu-wui-map"; + }; +}; diff --git a/dts/arm/nuvoton/npck/npck3/npck3-pinctrl.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-pinctrl.dtsi new file mode 100644 index 00000000000..e187bc15a80 --- /dev/null +++ b/dts/arm/nuvoton/npck/npck3/npck3-pinctrl.dtsi @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /* Prebuild nodes for peripheral device's characteristics (Optional) */ + /omit-if-no-ref/ shd_bkp_flash_tris_off: devctl-fiu-ext-tris-off { + dev-ctl = <0x0 6 1 0x00>; + }; + + /omit-if-no-ref/ shd_bkp_flash_tris_on: devctl-fiu-ext-tris-on { + dev-ctl = <0x0 6 1 0x01>; + }; + + /omit-if-no-ref/ pvt_flash_tris_off: devctl-fiu-int-tris-off { + dev-ctl = <0x0 7 1 0x00>; + }; + + /omit-if-no-ref/ pvt_flash_tris_on: devctl-fiu-int-tris-on { + dev-ctl = <0x0 7 1 0x01>; + }; + + /omit-if-no-ref/ peci_en: devctl-peci-en { + dev-ctl = <0x6 7 1 0x01>; + }; + + /* Prebuild nodes for peripheral device's pin-muxing and pad properties */ + /* Flash Interface Unit (FIU) */ + /omit-if-no-ref/ fiu_shd_io0_io1_clk_cs_gpc5_c4_c7_c6: periph-fiu-shd { + pinmux = <&alt0_shd1_spi>; + }; + + /omit-if-no-ref/ fiu_pvt_flash_sl: periph-fiu-int { + pinmux = <&alt0_pvt_spi_sl>; + }; + + /omit-if-no-ref/ fiu_shd_bkp_flash_sl: periph-fiu-ext { + pinmux = <&alt0_shd_bkp_spi_sl>; + }; + + /omit-if-no-ref/ fiu_shd_quad_io2_io3_gp81_77: periph-fiu-shd-quad { + pinmux = <&alt0_shdf_spi_quad>; + }; + + /omit-if-no-ref/ fiu_pvt_quad_sl: periph-fiu-pvt-quad { + pinmux = <&alt0_shdf_spi_quad>; + }; + + /omit-if-no-ref/ fiu_shd_cs_gpc6_sl: periph-fiu-shd-cs1 { + pinmux = <&alt4_noshd2_spi>; + }; + + /omit-if-no-ref/ fiu_bkp_cs_gp94_sl: periph-fiu-shd-cs2 { + pinmux = <&alt4_shd2_spi>; + }; + + /* Host peripheral interfaces */ + /omit-if-no-ref/ espi_lpc_gp10_f7: periph-lpc-espi { + pinmux = <&alt1_lpc_espi_def>; + }; + + /* I2C peripheral interfaces */ + /omit-if-no-ref/ i2c1_a_sda_scl_gp22_17: periph-i2c1-a { + pinmux = <&alt2_smb1a_sl>; + periph-pupd = <0x00 0>; + }; + + /omit-if-no-ref/ i2c1_b_sda_scl_gp74_73: periph-i2c1-b { + pinmux = <&alt2_smb1b_sl>; + periph-pupd = <0x00 1>; + }; + + /omit-if-no-ref/ i2c2_a_sda_scl_gp50_52: periph-i2c2-a { + pinmux = <&altc_smb2a_sl>; + periph-pupd = <0x00 2>; + }; + + /omit-if-no-ref/ i2c2_b_sda_scl_gpd5_d6: periph-i2c2-b { + pinmux = <&altc_smb2b_sl>; + periph-pupd = <0x00 3>; + }; + + /omit-if-no-ref/ i2c3_a_sda_scl_gp31_23: periph-i2c3-a { + pinmux = <&alta_smb3a_sl>; + periph-pupd = <0x00 4>; + }; + + /omit-if-no-ref/ i2c3_b_sda_scl_gpe1_e2: periph-i2c3-b { + pinmux = <&altc_smb3b_sl>; + periph-pupd = <0x00 5>; + }; + + /omit-if-no-ref/ i2c4_a_sda_scl_gp53_47: periph-i2c4-a { + pinmux = <&alta_smb4a_sl>; + periph-pupd = <0x00 6>; + }; + + /omit-if-no-ref/ i2c4_b_sda_scl_gp46_44: periph-i2c4-b { + pinmux = <&altc_smb4b_sl>; + periph-pupd = <0x00 7>; + }; + + /omit-if-no-ref/ i2c5_a_sda_scl_gpe3_e4: periph-i2c5-a { + pinmux = <&alta_smb5a_sl>; + periph-pupd = <0x01 0>; + }; + + /omit-if-no-ref/ i2c6_a_sda_scl_gpe6_25: periph-i2c6-a { + pinmux = <&alta_smb6a_sl>; + periph-pupd = <0x01 1>; + }; + + /* PWM peripheral interfaces */ + /omit-if-no-ref/ pwma_gp15: periph-pwm0 { + pinmux = <&alt5_a_pwm_sl>; + }; + + /omit-if-no-ref/ pwmb_gp21: periph-pwm1 { + pinmux = <&alt5_b_pwm_sl>; + }; + + /omit-if-no-ref/ pwmc_gp13: periph-pwm2 { + pinmux = <&alt5_c_pwm_sl>; + }; + + /omit-if-no-ref/ pwmd_gp32: periph-pwm3 { + pinmux = <&alt5_d_pwm_sl>; + }; + + /omit-if-no-ref/ pwmf_gp40: periph-pwm5 { + pinmux = <&alt5_f_pwm_sl>; + }; + + /omit-if-no-ref/ pwmi_gp72: periph-pwm8 { + pinmux = <&alt8_i_pwm_sl>; + }; + + /omit-if-no-ref/ pwmj_gpd3: periph-pwm9 { + pinmux = <&alt8_j_pwm_sl>; + }; + + /omit-if-no-ref/ pwmk_gp55: periph-pwm10 { + pinmux = <&alt8_k_pwm_sl>; + }; + + /* ADC peripheral interfaces. */ + /omit-if-no-ref/ adc0_chan0_gp90: periph-adc0-0 { + pinmux = <&alt6_adc0_sl>; + }; + + /omit-if-no-ref/ adc0_chan1_gp91: periph-adc0-1 { + pinmux = <&alt6_adc1_sl>; + }; + + /omit-if-no-ref/ adc0_chan2_gp92: periph-adc0-2 { + pinmux = <&alt6_adc2_sl>; + }; + + /omit-if-no-ref/ adc0_chan3_gp93: periph-adc0-3 { + pinmux = <&alt6_adc3_sl>; + }; + + /omit-if-no-ref/ adc0_chan4_gp05: periph-adc0-4 { + pinmux = <&alt6_adc4_sl>; + }; + + /omit-if-no-ref/ adc0_chan5_gp04: periph-adc0-5 { + pinmux = <&alt6_adc5_sl>; + }; + + /omit-if-no-ref/ adc0_chan6_gp03: periph-adc0-6 { + pinmux = <&alt6_adc6_sl>; + }; + + /omit-if-no-ref/ adc0_chan7_gp07: periph-adc0-7 { + pinmux = <&alt6_adc7_sl>; + }; + + /omit-if-no-ref/ adc0_chan8_gph2: periph-adc0-8 { + pinmux = <&alt11_adc8_sl>; + }; + + /omit-if-no-ref/ adc0_chan9_gph1: periph-adc0-9 { + pinmux = <&alt11_adc9_sl>; + }; + + /omit-if-no-ref/ adc0_chan10_gph0: periph-adc0-10 { + pinmux = <&alt11_adc10_sl>; + }; + + /omit-if-no-ref/ adc0_chan11_gpg7: periph-adc0-11 { + pinmux = <&alt11_adc11_sl>; + }; + + /* UART peripheral interfaces */ + /omit-if-no-ref/ uart1_sin_gp87: periph-uart1-sin { + pinmux = <&alt1_urti_sl>; + }; + + /omit-if-no-ref/ uart1_sout_gp83: periph-uart1-sout { + pinmux = <&alt1_urto1_sl>; + }; + + /* PS2 peripheral interfaces */ + /omit-if-no-ref/ ps2_2_dat_clk_gp26_27: periph-ps2-2 { + pinmux = <&alt4_ps2_2_sl>; + }; + + /omit-if-no-ref/ ps2_3_dat_clk_gp50_52: periph-ps2-3 { + pinmux = <&alt4_ps2_3_sl>; + }; + + /* Tachometer peripheral interfaces */ + /omit-if-no-ref/ ta1_1_in_gp56: periph-ta1-1 { + pinmux = <&alt3_ta1_1_sl>; + }; + + /omit-if-no-ref/ ta1_2_in_gpa0: periph-ta1-2 { + pinmux = <&alt3_ta1_2_sl>; + }; + + /omit-if-no-ref/ tb1_1_in_gp14: periph-tb1-1 { + pinmux = <&alt3_tb1_1_sl>; + }; + + /omit-if-no-ref/ tb1_2_in_gpa3: periph-tb1-2 { + pinmux = <&alt3_tb1_2_sl>; + }; + + /omit-if-no-ref/ ta2_1_in_gp20: periph-ta2-1 { + pinmux = <&alt3_ta2_1_sl>; + }; + + /omit-if-no-ref/ ta2_2_in_gpa4: periph-ta2-2 { + pinmux = <&alt10_ta2_2_sl>; + }; + + /omit-if-no-ref/ tb2_1_in_gp01: periph-tb2-1 { + pinmux = <&alt3_tb2_1_sl>; + }; + + /omit-if-no-ref/ tb2_2_in_gpa5: periph-tb2-2 { + pinmux = <&alt10_tb2_2_sl>; + }; + + /omit-if-no-ref/ ta3_1_in_gp51: periph-ta3-1 { + pinmux = <&alt3_ta3_1_sl>; + }; + + /omit-if-no-ref/ ta3_2_in_gpa6: periph-ta3-2 { + pinmux = <&alt10_ta3_2_sl>; + }; + + /omit-if-no-ref/ tb3_1_in_gp36: periph-tb3-1 { + pinmux = <&alt3_tb3_1_sl>; + }; + + /omit-if-no-ref/ tb3_2_in_gpa7: periph-tb3-2 { + pinmux = <&alt10_tb3_2_sl>; + }; + + /omit-if-no-ref/ ta4_in_gpe0: periph-ta4 { + pinmux = <&alt10_ta4_sl>; + }; + + /omit-if-no-ref/ tb4_in_gp60: periph-tb4 { + pinmux = <&alt10_tb4_sl>; + }; + + /omit-if-no-ref/ ta5_in_gpb0: periph-ta5 { + pinmux = <&alt10_ta5_sl>; + }; + + /omit-if-no-ref/ tb5_in_gp61: periph-tb5 { + pinmux = <&alt10_tb5_sl>; + }; + + /* Keyboard peripheral interfaces. */ + /omit-if-no-ref/ ksi0_1_2_3_gpa0_a1_a2_a3: periph-kbscan-ksi0_1_2_3 { + pinmux = <&alt9_no_ksi0_ksi1_ksi2_ksi3_sl>; + }; + + /omit-if-no-ref/ ksi4_5_gpa4_a5: periph-kbscan-ksi4_5 { + pinmux = <&alt9_no_ksi4_ksi5_sl>; + }; + + /omit-if-no-ref/ ksi6_7_gpa6_a7: periph-kbscan-ksi6_7 { + pinmux = <&alt9_no_ksi6_ksi7_sl>; + }; + + /omit-if-no-ref/ kso00_01_02_03_gpb0_b1_b2_b3: periph-kbscan-kso00_01_02_03 { + pinmux = <&alt9_no_kso0_kso1_kso2_kso3_sl>; + }; + + /omit-if-no-ref/ kso04_05_06_07_gpb4_b5_b6_b7: periph-kbscan-kso04_05_06_07 { + pinmux = <&alt9_no_kso4_kso5_kso6_kso7_sl>; + }; + + /omit-if-no-ref/ kso08_09_gpc0_c1: periph-kbscan-kso08_09 { + pinmux = <&alt9_no_kso8_kso9_sl>; + }; + + /omit-if-no-ref/ kso10_11_gpc2_c3: periph-kbscan-kso10_11 { + pinmux = <&alt9_no_kso10_kso11_sl>; + }; + + /omit-if-no-ref/ kso12_gp64: periph-kbscan-kso12 { + pinmux = <&alt7_kso12_sl_def>; + }; + + /omit-if-no-ref/ kso13_gp63: periph-kbscan-kso13 { + pinmux = <&alt7_kso13_sl_def>; + }; + + /omit-if-no-ref/ kso14_gp62: periph-kbscan-kso14 { + pinmux = <&alt7_kso14_sl_def>; + }; + + /omit-if-no-ref/ kso15_gp61: periph-kbscan-kso15 { + pinmux = <&alt7_kso15_sl_def>; + }; + + /omit-if-no-ref/ kso16_gp60: periph-kbscan-kso16 { + pinmux = <&alt7_kso16_sl>; + }; + + /omit-if-no-ref/ kso17_gp57: periph-kbscan-kso17 { + pinmux = <&alt7_kso17_sl>; + }; + + /* PSL peripheral interfaces */ + /omit-if-no-ref/ psl_in0_gpstb11: periph-psl-in0 { + pinmux = <&altf_psl_in0_en_def>; + psl-offset = <1>; + psl-polarity = <&altcx_psl_in0_ahi>; + }; + + /omit-if-no-ref/ psl_in1_gpstb12: periph-psl-in1 { + pinmux = <&altf_psl_in1_en_def>; + psl-offset = <2>; + psl-polarity = <&altcx_psl_in1_ahi>; + }; + + /omit-if-no-ref/ psl_in2_gpstb13: periph-psl-in2 { + pinmux = <&altf_psl_in2_en>; + psl-offset = <3>; + psl-polarity = <&altcx_psl_in2_ahi>; + }; + + /omit-if-no-ref/ psl_in3_gpstb14: periph-psl-in3 { + pinmux = <&altf_psl_in3_en>; + psl-offset = <4>; + psl-polarity = <&altcx_psl_in3_ahi>; + }; + + /omit-if-no-ref/ psl_in4_gpstb15: periph-psl-in4 { + pinmux = <&altf_psl_in4_en>; + psl-offset = <5>; + psl-polarity = <&altcx_psl_in4_ahi>; + }; + + /omit-if-no-ref/ psl_in5_gpstb16: periph-psl-in5 { + pinmux = <&altf_psl_in5_en>; + psl-offset = <6>; + psl-polarity = <&altcx_psl_in5_ahi>; + }; + + /omit-if-no-ref/ psl_out_gpstb17: periph-psl-out { + pinmux = <&altf_psl_out_en_def>; + }; + + /omit-if-no-ref/ psl_out_fw_high: periph-psl-out-inactive-high { + pinmux = <&altdx_psl_fw_ctl_high>; + }; + + /omit-if-no-ref/ psl_out_fw_low: periph-psl-out-inactive-low { + pinmux = <&altdx_psl_fw_ctl_low>; + }; + + /omit-if-no-ref/ psl_out_fw_ctl_en: periph-psl-out-fw-ctl { + pinmux = <&altdx_psl_out_gpo>; + }; + + /* Miscellaneous peripheral interfaces */ + /omit-if-no-ref/ clkout_gp55: periph-clkout { + pinmux = <&alt0_ckout_sl>; + }; + + /* Serial UART peripheral interfaces */ + /omit-if-no-ref/ huart_sin1_gp34: periph-host-uart_sin1 { + pinmux = <&alt0_sp1i_sl>; + }; + + /omit-if-no-ref/ huart_sout1_gp67: periph-host-uart_sout1 { + pinmux = <&alt0_sp1o_sl>; + }; + + /omit-if-no-ref/ huart_sin2_gp87: periph-host-uart_sin2 { + pinmux = <&altb_sp2i_sl>; + }; + + /omit-if-no-ref/ huart_sout2_gp83: periph-host-uart_sout2 { + pinmux = <&altb_sp2o_sl>; + }; +}; diff --git a/dts/arm/nuvoton/npck3m8k.dtsi b/dts/arm/nuvoton/npck3m8k.dtsi new file mode 100644 index 00000000000..fdd860b9495 --- /dev/null +++ b/dts/arm/nuvoton/npck3m8k.dtsi @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "npck/npck3.dtsi" + +/ { + flash0: flash@10058000 { + reg = <0x10058000 DT_SIZE_K(416)>; + }; + + flash1: flash@60000000 { + reg = <0x60000000 DT_SIZE_K(512)>; + }; + + sram0: memory@200c0000 { + compatible = "mmio-sram"; + reg = <0x200C0000 DT_SIZE_K(62)>; + }; + + /* RAM space used by Booter */ + bootloader_ram: memory@200c7800 { + compatible = "mmio-sram"; + reg = <0x200C7800 DT_SIZE_K(2)>; + }; + + soc-id { + device-id = <0x22>; + }; +};