drivers: clock_control: stm32: enable PWR clock unconditionally
Enable PWR clock unconditionally for L4, L5 and U5 like it is done on other stm32 series Fixes #37781 Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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2 changed files with 7 additions and 6 deletions
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@ -60,9 +60,10 @@ static void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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*/
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*/
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void config_enable_default_clocks(void)
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void config_enable_default_clocks(void)
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{
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{
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#if STM32_LSE_CLOCK
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/* Enable the power interface clock */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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#if STM32_LSE_CLOCK
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if (!LL_PWR_IsEnabledBkUpAccess()) {
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if (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Enable write access to Backup domain */
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/* Enable write access to Backup domain */
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LL_PWR_EnableBkUpAccess();
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LL_PWR_EnableBkUpAccess();
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@ -48,6 +48,11 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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*/
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*/
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void config_enable_default_clocks(void)
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void config_enable_default_clocks(void)
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{
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{
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#ifdef LL_APB1_GRP1_PERIPH_PWR
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#endif
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#if STM32_LSE_CLOCK
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#if STM32_LSE_CLOCK
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/* LSE belongs to the back-up domain, enable access.*/
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/* LSE belongs to the back-up domain, enable access.*/
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@ -57,11 +62,6 @@ void config_enable_default_clocks(void)
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#endif
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#endif
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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#ifdef LL_APB1_GRP1_PERIPH_PWR
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#endif
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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LL_PWR_EnableBkUpAccess();
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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