drivers: display: ili9xxx: add support for ILI9488 controller

Add support for the ILI9488 display controller.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2020-10-26 20:01:42 +01:00 committed by Maureen Helm
commit 4812bb5175
6 changed files with 233 additions and 0 deletions

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@ -14,6 +14,7 @@ if (CONFIG_ILI9XXX)
zephyr_sources(display_ili9xxx.c)
endif()
zephyr_sources_ifdef(CONFIG_ILI9340 display_ili9340.c)
zephyr_sources_ifdef(CONFIG_ILI9488 display_ili9488.c)
zephyr_sources_ifdef(CONFIG_MICROBIT_DISPLAY
mb_display.c

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@ -1,6 +1,7 @@
# ILI9XXX display driver configuration options
# Copyright (c) 2017 Jan Van Winkel <jan.van_winkel@dxplore.eu>
# Copyright (c) 2020 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
config ILI9XXX
@ -14,3 +15,10 @@ config ILI9340
select ILI9XXX
help
Enable driver for ILI9340 display driver.
config ILI9488
bool "ILI9488 display driver"
depends on SPI
select ILI9XXX
help
Enable driver for ILI9488 display driver.

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@ -0,0 +1,70 @@
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "display_ili9488.h"
#include "display_ili9xxx.h"
#include <logging/log.h>
LOG_MODULE_REGISTER(display_ili9488, CONFIG_DISPLAY_LOG_LEVEL);
int ili9488_regs_init(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
const struct ili9488_regs *regs = config->regs;
int r;
LOG_HEXDUMP_DBG(regs->frmctr1, ILI9488_FRMCTR1_LEN, "FRMCTR1");
r = ili9xxx_transmit(dev, ILI9488_FRMCTR1, regs->frmctr1,
ILI9488_FRMCTR1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->disctrl, ILI9488_DISCTRL_LEN, "DISCTRL");
r = ili9xxx_transmit(dev, ILI9488_DISCTRL, regs->disctrl,
ILI9488_DISCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9488_PWCTRL1_LEN, "PWCTRL1");
r = ili9xxx_transmit(dev, ILI9488_PWCTRL1, regs->pwctrl1,
ILI9488_PWCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9488_PWCTRL2_LEN, "PWCTRL2");
r = ili9xxx_transmit(dev, ILI9488_PWCTRL2, regs->pwctrl2,
ILI9488_PWCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl, ILI9488_VMCTRL_LEN, "VMCTRL");
r = ili9xxx_transmit(dev, ILI9488_VMCTRL, regs->vmctrl,
ILI9488_VMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pgamctrl, ILI9488_PGAMCTRL_LEN, "PGAMCTRL");
r = ili9xxx_transmit(dev, ILI9488_PGAMCTRL, regs->pgamctrl,
ILI9488_PGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ngamctrl, ILI9488_NGAMCTRL_LEN, "NGAMCTRL");
r = ili9xxx_transmit(dev, ILI9488_NGAMCTRL, regs->ngamctrl,
ILI9488_NGAMCTRL_LEN);
if (r < 0) {
return r;
}
return 0;
}

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@ -0,0 +1,65 @@
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_
#include <device.h>
/* Commands/registers. */
#define ILI9488_FRMCTR1 0xB1
#define ILI9488_DISCTRL 0xB6
#define ILI9488_PWCTRL1 0xC0
#define ILI9488_PWCTRL2 0xC1
#define ILI9488_VMCTRL 0xC5
#define ILI9488_PGAMCTRL 0xE0
#define ILI9488_NGAMCTRL 0xE1
/* Commands/registers length. */
#define ILI9488_FRMCTR1_LEN 2U
#define ILI9488_DISCTRL_LEN 3U
#define ILI9488_PWCTRL1_LEN 2U
#define ILI9488_PWCTRL2_LEN 1U
#define ILI9488_VMCTRL_LEN 4U
#define ILI9488_PGAMCTRL_LEN 15U
#define ILI9488_NGAMCTRL_LEN 15U
/** X resolution (pixels). */
#define ILI9488_X_RES 320U
/** Y resolution (pixels). */
#define ILI9488_Y_RES 480U
/** ILI9488 registers to be initialized. */
struct ili9488_regs {
uint8_t frmctr1[ILI9488_FRMCTR1_LEN];
uint8_t disctrl[ILI9488_DISCTRL_LEN];
uint8_t pwctrl1[ILI9488_PWCTRL1_LEN];
uint8_t pwctrl2[ILI9488_PWCTRL2_LEN];
uint8_t vmctrl[ILI9488_VMCTRL_LEN];
uint8_t pgamctrl[ILI9488_PGAMCTRL_LEN];
uint8_t ngamctrl[ILI9488_NGAMCTRL_LEN];
};
/* Initializer macro for ILI9488 registers. */
#define ILI9488_REGS_INIT(n) \
static const struct ili9488_regs ili9xxx_regs_##n = { \
.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9488), frmctr1), \
.disctrl = DT_PROP(DT_INST(n, ilitek_ili9488), disctrl), \
.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl1), \
.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl2), \
.vmctrl = DT_PROP(DT_INST(n, ilitek_ili9488), vmctrl), \
.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), pgamctrl), \
.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), ngamctrl), \
}
/**
* @brief Initialize ILI9488 registers with DT values.
*
* @param dev ILI9488 device instance
* @return 0 on success, errno otherwise.
*/
int ili9488_regs_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_ */

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@ -489,3 +489,8 @@ static const struct display_driver_api ili9xxx_api = {
#include "display_ili9340.h"
DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9340);
#endif
#ifdef CONFIG_ILI9488
#include "display_ili9488.h"
DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9488);
#endif

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@ -0,0 +1,84 @@
# Copyright (c) 2020, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
description: ILI9488 320x480 display controller
compatible: "ilitek,ili9488"
include: ilitek,ili9xxx-common.yaml
properties:
frmctr1:
type: uint8-array
default: [0xb0, 0x11]
description:
Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
disctrl:
type: uint8-array
default: [0x02, 0x02, 0x3b]
description:
Display function control (DISCTRL) register value. Note that changing
default SS bit value (0) may interfere with display rotation.
pwctrl1:
type: uint8-array
default: [0x0e, 0x0e]
description:
Power control 1 (PWCTRL1) register values.
pwctrl2:
type: uint8-array
default: [0x43]
description:
Power control 2 (PWCTRL2) register values.
vmctrl:
type: uint8-array
default: [0x00, 0x40, 0x00, 0x40]
description:
VCOM control (VMCTRL) register values.
pgamctrl:
type: uint8-array
default: [
0x0f,
0x1f,
0x1c,
0x0b,
0x0e,
0x09,
0x48,
0x99,
0x38,
0x0a,
0x14,
0x06,
0x11,
0x09,
0x00
]
description:
Positive gamma correction (PGAMCTRL) register values.
ngamctrl:
type: uint8-array
default: [
0x0f,
0x36,
0x2e,
0x09,
0x0a,
0x04,
0x46,
0x66,
0x37,
0x06,
0x10,
0x04,
0x24,
0x20,
0x00
]
description:
Negative gamma correction (NGAMCTRL) register values.