drivers: display: ili9xxx: add support for ILI9488 controller
Add support for the ILI9488 display controller. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
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6 changed files with 233 additions and 0 deletions
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@ -14,6 +14,7 @@ if (CONFIG_ILI9XXX)
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zephyr_sources(display_ili9xxx.c)
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endif()
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zephyr_sources_ifdef(CONFIG_ILI9340 display_ili9340.c)
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zephyr_sources_ifdef(CONFIG_ILI9488 display_ili9488.c)
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zephyr_sources_ifdef(CONFIG_MICROBIT_DISPLAY
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mb_display.c
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@ -1,6 +1,7 @@
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# ILI9XXX display driver configuration options
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# Copyright (c) 2017 Jan Van Winkel <jan.van_winkel@dxplore.eu>
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# Copyright (c) 2020 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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config ILI9XXX
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@ -14,3 +15,10 @@ config ILI9340
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select ILI9XXX
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help
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Enable driver for ILI9340 display driver.
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config ILI9488
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bool "ILI9488 display driver"
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depends on SPI
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select ILI9XXX
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help
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Enable driver for ILI9488 display driver.
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70
drivers/display/display_ili9488.c
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70
drivers/display/display_ili9488.c
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@ -0,0 +1,70 @@
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/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "display_ili9488.h"
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#include "display_ili9xxx.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(display_ili9488, CONFIG_DISPLAY_LOG_LEVEL);
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int ili9488_regs_init(const struct device *dev)
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{
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const struct ili9xxx_config *config = dev->config;
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const struct ili9488_regs *regs = config->regs;
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int r;
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LOG_HEXDUMP_DBG(regs->frmctr1, ILI9488_FRMCTR1_LEN, "FRMCTR1");
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r = ili9xxx_transmit(dev, ILI9488_FRMCTR1, regs->frmctr1,
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ILI9488_FRMCTR1_LEN);
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if (r < 0) {
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return r;
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}
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LOG_HEXDUMP_DBG(regs->disctrl, ILI9488_DISCTRL_LEN, "DISCTRL");
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r = ili9xxx_transmit(dev, ILI9488_DISCTRL, regs->disctrl,
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ILI9488_DISCTRL_LEN);
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if (r < 0) {
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return r;
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}
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LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9488_PWCTRL1_LEN, "PWCTRL1");
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r = ili9xxx_transmit(dev, ILI9488_PWCTRL1, regs->pwctrl1,
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ILI9488_PWCTRL1_LEN);
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if (r < 0) {
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return r;
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}
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LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9488_PWCTRL2_LEN, "PWCTRL2");
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r = ili9xxx_transmit(dev, ILI9488_PWCTRL2, regs->pwctrl2,
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ILI9488_PWCTRL2_LEN);
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if (r < 0) {
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return r;
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}
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LOG_HEXDUMP_DBG(regs->vmctrl, ILI9488_VMCTRL_LEN, "VMCTRL");
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r = ili9xxx_transmit(dev, ILI9488_VMCTRL, regs->vmctrl,
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ILI9488_VMCTRL_LEN);
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if (r < 0) {
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return r;
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}
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LOG_HEXDUMP_DBG(regs->pgamctrl, ILI9488_PGAMCTRL_LEN, "PGAMCTRL");
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r = ili9xxx_transmit(dev, ILI9488_PGAMCTRL, regs->pgamctrl,
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ILI9488_PGAMCTRL_LEN);
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if (r < 0) {
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return r;
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}
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LOG_HEXDUMP_DBG(regs->ngamctrl, ILI9488_NGAMCTRL_LEN, "NGAMCTRL");
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r = ili9xxx_transmit(dev, ILI9488_NGAMCTRL, regs->ngamctrl,
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ILI9488_NGAMCTRL_LEN);
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if (r < 0) {
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return r;
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}
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return 0;
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}
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65
drivers/display/display_ili9488.h
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65
drivers/display/display_ili9488.h
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@ -0,0 +1,65 @@
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/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_
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#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_
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#include <device.h>
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/* Commands/registers. */
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#define ILI9488_FRMCTR1 0xB1
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#define ILI9488_DISCTRL 0xB6
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#define ILI9488_PWCTRL1 0xC0
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#define ILI9488_PWCTRL2 0xC1
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#define ILI9488_VMCTRL 0xC5
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#define ILI9488_PGAMCTRL 0xE0
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#define ILI9488_NGAMCTRL 0xE1
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/* Commands/registers length. */
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#define ILI9488_FRMCTR1_LEN 2U
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#define ILI9488_DISCTRL_LEN 3U
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#define ILI9488_PWCTRL1_LEN 2U
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#define ILI9488_PWCTRL2_LEN 1U
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#define ILI9488_VMCTRL_LEN 4U
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#define ILI9488_PGAMCTRL_LEN 15U
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#define ILI9488_NGAMCTRL_LEN 15U
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/** X resolution (pixels). */
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#define ILI9488_X_RES 320U
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/** Y resolution (pixels). */
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#define ILI9488_Y_RES 480U
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/** ILI9488 registers to be initialized. */
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struct ili9488_regs {
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uint8_t frmctr1[ILI9488_FRMCTR1_LEN];
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uint8_t disctrl[ILI9488_DISCTRL_LEN];
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uint8_t pwctrl1[ILI9488_PWCTRL1_LEN];
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uint8_t pwctrl2[ILI9488_PWCTRL2_LEN];
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uint8_t vmctrl[ILI9488_VMCTRL_LEN];
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uint8_t pgamctrl[ILI9488_PGAMCTRL_LEN];
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uint8_t ngamctrl[ILI9488_NGAMCTRL_LEN];
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};
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/* Initializer macro for ILI9488 registers. */
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#define ILI9488_REGS_INIT(n) \
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static const struct ili9488_regs ili9xxx_regs_##n = { \
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.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9488), frmctr1), \
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.disctrl = DT_PROP(DT_INST(n, ilitek_ili9488), disctrl), \
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.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl1), \
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.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl2), \
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.vmctrl = DT_PROP(DT_INST(n, ilitek_ili9488), vmctrl), \
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.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), pgamctrl), \
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.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), ngamctrl), \
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}
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/**
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* @brief Initialize ILI9488 registers with DT values.
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*
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* @param dev ILI9488 device instance
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* @return 0 on success, errno otherwise.
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*/
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int ili9488_regs_init(const struct device *dev);
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#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_ */
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@ -489,3 +489,8 @@ static const struct display_driver_api ili9xxx_api = {
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#include "display_ili9340.h"
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DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9340);
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#endif
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#ifdef CONFIG_ILI9488
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#include "display_ili9488.h"
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DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9488);
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#endif
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84
dts/bindings/display/ilitek,ili9488.yaml
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84
dts/bindings/display/ilitek,ili9488.yaml
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# Copyright (c) 2020, Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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description: ILI9488 320x480 display controller
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compatible: "ilitek,ili9488"
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include: ilitek,ili9xxx-common.yaml
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properties:
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frmctr1:
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type: uint8-array
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default: [0xb0, 0x11]
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description:
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Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
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disctrl:
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type: uint8-array
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default: [0x02, 0x02, 0x3b]
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description:
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Display function control (DISCTRL) register value. Note that changing
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default SS bit value (0) may interfere with display rotation.
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pwctrl1:
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type: uint8-array
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default: [0x0e, 0x0e]
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description:
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Power control 1 (PWCTRL1) register values.
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pwctrl2:
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type: uint8-array
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default: [0x43]
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description:
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Power control 2 (PWCTRL2) register values.
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vmctrl:
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type: uint8-array
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default: [0x00, 0x40, 0x00, 0x40]
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description:
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VCOM control (VMCTRL) register values.
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pgamctrl:
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type: uint8-array
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default: [
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0x0f,
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0x1f,
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0x1c,
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0x0b,
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0x0e,
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0x09,
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0x48,
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0x99,
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0x38,
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0x0a,
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0x14,
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0x06,
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0x11,
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0x09,
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0x00
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]
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description:
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Positive gamma correction (PGAMCTRL) register values.
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ngamctrl:
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type: uint8-array
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default: [
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0x0f,
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0x36,
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0x2e,
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0x09,
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0x0a,
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0x04,
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0x46,
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0x66,
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0x37,
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0x06,
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0x10,
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0x04,
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0x24,
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0x20,
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0x00
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]
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description:
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Negative gamma correction (NGAMCTRL) register values.
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