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drivers/pinctrl: stm32: Allow plain GPIO configuration

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Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-18 10:58:29 +01:00 • committed by Marti Bolivar
commit 48039bc555
5 changed files with 65 additions and 17 deletions
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50
drivers/gpio/gpio_stm32.c
View file

@ -123,7 +123,7 @@ static void gpio_stm32_configure_raw(const struct device *dev, int pin,
int pin_ll = stm32_pinval_get(pin);
#ifdef CONFIG_SOC_SERIES_STM32F1X
ARG_UNUSED(altf);
ARG_UNUSED(func);
uint32_t temp = conf &
(STM32_MODE_INOUT_MASK << STM32_MODE_INOUT_SHIFT);
@ -211,9 +211,9 @@ static void gpio_stm32_configure_raw(const struct device *dev, int pin,
if (mode == STM32_MODER_ALT_MODE) {
if (pin < 8) {
LL_GPIO_SetAFPin_0_7(gpio, pin_ll, altf);
LL_GPIO_SetAFPin_0_7(gpio, pin_ll, func);
} else {
LL_GPIO_SetAFPin_8_15(gpio, pin_ll, altf);
LL_GPIO_SetAFPin_8_15(gpio, pin_ll, func);
}
}
@ -224,20 +224,6 @@ static void gpio_stm32_configure_raw(const struct device *dev, int pin,
}
int gpio_stm32_configure(const struct device *dev, int pin, int conf, int func)
{
int ret;
ret = pm_device_runtime_get(dev);
if (ret < 0) {
return ret;
}
gpio_stm32_configure_raw(dev, pin, conf, func);
return pm_device_runtime_put(dev);
}
/**
* @brief GPIO port clock handling
*/
@ -461,6 +447,36 @@ static int gpio_stm32_port_toggle_bits(const struct device *dev,
return 0;
}
#ifdef CONFIG_SOC_SERIES_STM32F1X
#define IS_GPIO_OUT GPIO_OUT
#else
#define IS_GPIO_OUT STM32_GPIO
#endif
int gpio_stm32_configure(const struct device *dev, int pin, int conf, int func)
{
int ret;
ret = pm_device_runtime_get(dev);
if (ret < 0) {
return ret;
}
gpio_stm32_configure_raw(dev, pin, conf, func);
if (func == IS_GPIO_OUT) {
uint32_t gpio_out = conf & (STM32_ODR_MASK << STM32_ODR_SHIFT);
if (gpio_out == STM32_ODR_1) {
gpio_stm32_port_set_bits_raw(dev, BIT(pin));
} else if (gpio_out == STM32_ODR_0) {
gpio_stm32_port_clear_bits_raw(dev, BIT(pin));
}
}
return pm_device_runtime_put(dev);
}
/**
* @brief Configure pin or port
*/

10
drivers/pinctrl/pinctrl_stm32.c
View file

@ -224,6 +224,8 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
} else {
pin_cgf = pin_cgf | STM32_CNF_IN_PUPD;
}
} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_OUT) {
pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT;
} else {
/* Not supported */
__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
@ -233,6 +235,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
pin_cgf = pins[i].pincfg | STM32_MODER_ALT_MODE;
} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) {
pin_cgf = STM32_MODER_ANALOG_MODE;
} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_GPIO) {
uint32_t gpio_out = pins[i].pincfg &
(STM32_ODR_MASK << STM32_ODR_SHIFT);
if (gpio_out != 0) {
pin_cgf = pins[i].pincfg | STM32_MODER_OUTPUT_MODE;
} else {
pin_cgf = pins[i].pincfg | STM32_MODER_INPUT_MODE;
}
} else {
/* Not supported */
__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));

8
include/dt-bindings/pinctrl/stm32-pinctrl.h
View file

@ -32,6 +32,7 @@
#define STM32_AF14 0xe
#define STM32_AF15 0xf
#define STM32_ANALOG 0x10
#define STM32_GPIO 0x11
/**
* @brief Macro to generate pinmux int using port, pin number and mode arguments
@ -74,6 +75,7 @@
* GPIO Output type [ 6 ]
* GPIO Speed [ 7 : 8 ]
* GPIO PUPD config [ 9 : 10 ]
* GPIO Output data [ 11 ]
*
* Applicable to STM32F3, STM32F4, STM32L4 series
*/
@ -107,4 +109,10 @@
#define STM32_PUPDR_MASK 0x3
#define STM32_PUPDR_SHIFT 9
/* GPIO plain output value */
#define STM32_ODR_0 (0x0<<STM32_ODR_SHIFT)
#define STM32_ODR_1 (0x1<<STM32_ODR_SHIFT)
#define STM32_ODR_MASK 0x1
#define STM32_ODR_SHIFT 11
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_ */

8
include/dt-bindings/pinctrl/stm32f1-pinctrl.h
View file

@ -55,6 +55,7 @@
#define ALTERNATE 0x0 /* Alternate function output */
#define GPIO_IN 0x1 /* Input */
#define ANALOG 0x2 /* Analog */
#define GPIO_OUT 0x3 /* Output */
/**
* @brief PIN configuration bitfield
@ -67,6 +68,7 @@
* GPIO Output PP/OD [ 5 ]
* GPIO Output AF/GP [ 6 ]
* GPIO PUPD Config [ 7 : 8 ]
* GPIO ODR [ 9 ]
*
* Applicable to STM32F1 series
*/
@ -108,4 +110,10 @@
#define STM32_PUPD_MASK 0x3
#define STM32_PUPD_SHIFT 7
/* GPIO plain output value */
#define STM32_ODR_0 (0x0<<STM32_ODR_SHIFT)
#define STM32_ODR_1 (0x1<<STM32_ODR_SHIFT)
#define STM32_ODR_MASK 0x1
#define STM32_ODR_SHIFT 9
#endif /* ZEPHYR_STM32_PINCTRLF1_H_ */

6
soc/arm/st_stm32/common/pinctrl_soc.h
View file

@ -51,6 +51,8 @@ typedef struct pinctrl_soc_pin {
#define STM32_PULL_DOWN 0x2
#define STM32_PUSH_PULL 0x0
#define STM32_OPEN_DRAIN 0x1
#define STM32_OUTPUT_LOW 0x0
#define STM32_OUTPUT_HIGH 0x1
#ifdef CONFIG_SOC_SERIES_STM32F1X
/**
@ -64,6 +66,8 @@ typedef struct pinctrl_soc_pin {
((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPD_SHIFT) | \
((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_CNF_OUT_0_SHIFT) | \
((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_CNF_OUT_0_SHIFT) | \
((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \
((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << STM32_MODE_OSPEED_SHIFT))
#else
/**
@ -77,6 +81,8 @@ typedef struct pinctrl_soc_pin {
((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPDR_SHIFT) | \
((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_OTYPER_SHIFT) | \
((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_OTYPER_SHIFT) | \
((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \
((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << STM32_OSPEEDR_SHIFT))
#endif /* CONFIG_SOC_SERIES_STM32F1X */