diff --git a/arch/arm/soc/st_stm32/stm32f0/dts.fixup b/arch/arm/soc/st_stm32/stm32f0/dts.fixup
index bab0ea4c5af..1842b14e12b 100644
--- a/arch/arm/soc/st_stm32/stm32f0/dts.fixup
+++ b/arch/arm/soc/st_stm32/stm32f0/dts.fixup
@@ -39,4 +39,12 @@
 #define FLASH_DEV_BASE_ADDRESS		        ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
 #define FLASH_DEV_NAME			        ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL
 
+#define CONFIG_USB_BASE_ADDRESS		ST_STM32_USB_40005C00_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_USB_40005C00_IRQ_USB
+#define CONFIG_USB_IRQ_PRI			ST_STM32_USB_40005C00_IRQ_USB_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_NUM_IN_ENDPOINTS		ST_STM32_USB_40005C00_NUM_IN_ENDPOINTS
+#define CONFIG_USB_NUM_OUT_ENDPOINTS		ST_STM32_USB_40005C00_NUM_OUT_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_USB_40005C00_RAM_SIZE
+
 /* End of SoC Level DTS fixup file */
diff --git a/arch/arm/soc/st_stm32/stm32f0/soc.c b/arch/arm/soc/st_stm32/stm32f0/soc.c
index 292faac9b3c..746ccce1478 100644
--- a/arch/arm/soc/st_stm32/stm32f0/soc.c
+++ b/arch/arm/soc/st_stm32/stm32f0/soc.c
@@ -60,6 +60,17 @@ uint32_t HAL_GetTick(void)
 	return k_uptime_get_32();
 }
 
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ *	  on variable incremented.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @return None
+ */
+void HAL_Delay(__IO uint32_t Delay)
+{
+	k_sleep(Delay);
+}
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c
index b6090193a23..086a8b66208 100644
--- a/drivers/usb/device/usb_dc_stm32.c
+++ b/drivers/usb/device/usb_dc_stm32.c
@@ -209,6 +209,20 @@ static int usb_dc_stm32_clock_enable(void)
 #endif /* USB */
 	};
 
+	/*
+	 * Some SoCs in STM32F0/L0/L4 series disable USB clock by default.
+	 * We force USB clock source to PLL clock for this SoCs.
+	 * Example reference manual RM0360 for STM32F030x4/x6/x8/xC and
+	 * STM32F070x6/xB.
+	 */
+#ifdef LL_RCC_USB_CLKSOURCE_NONE
+	if (LL_RCC_PLL_IsReady()) {
+		LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL);
+	} else {
+		SYS_LOG_ERR("Unable to set USB clock source to PLL.");
+	}
+#endif /* LL_RCC_USB_CLKSOURCE_NONE */
+
 	clock_control_on(clk, (clock_control_subsys_t *)&pclken);
 
 	return 0;
@@ -290,6 +304,14 @@ int usb_dc_attach(void)
 
 	SYS_LOG_DBG("");
 
+	/*
+	 * For STM32F0 series SoCs on QFN28 and TSSOP20 packages enable PIN
+	 * pair PA11/12 mapped instead of PA9/10 (e.g. stm32f070x6)
+	 */
+#if defined(CONFIG_SOC_SERIES_STM32F0X) && defined(SYSCFG_CFGR1_PA11_PA12_RMP)
+	LL_SYSCFG_EnablePinRemap();
+#endif
+
 	ret = usb_dc_stm32_clock_enable();
 	if (ret) {
 		return ret;
diff --git a/dts/arm/st/stm32f070.dtsi b/dts/arm/st/stm32f070.dtsi
index 0694048f464..312f16e3991 100644
--- a/dts/arm/st/stm32f070.dtsi
+++ b/dts/arm/st/stm32f070.dtsi
@@ -17,5 +17,18 @@
 			status = "disabled";
 			label = "SPI_2";
 		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			num-in-endpoints = <0>;
+			num-out-endpoints = <0>;
+			ram-size = <1024>;
+			status = "disabled";
+			label= "USB";
+		};
 	};
 };
diff --git a/dts/arm/st/stm32f072.dtsi b/dts/arm/st/stm32f072.dtsi
index 673b74f9d47..d17754c878c 100644
--- a/dts/arm/st/stm32f072.dtsi
+++ b/dts/arm/st/stm32f072.dtsi
@@ -29,5 +29,18 @@
 			status = "disabled";
 			label = "SPI_2";
 		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			num-in-endpoints = <0>;
+			num-out-endpoints = <0>;
+			ram-size = <1024>;
+			status = "disabled";
+			label= "USB";
+		};
 	};
 };