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soc: nuvoton: numaker: add support for m55m1x series

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Add initial support for nuvoton numaker m55m1x SoC series
including basic init and device tree source include.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This commit is contained in:
cyliang tw 2025-02-20 14:48:02 +08:00 • committed by Fabio Baltieri
commit 47dfd857f9
15 changed files with 1329 additions and 0 deletions
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14
soc/nuvoton/numaker/m55m1x/CMakeLists.txt Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_include_directories(.)
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)
zephyr_linker_sources(SECTIONS sections.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

24
soc/nuvoton/numaker/m55m1x/Kconfig Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_M55M1X
select ARM
select CPU_CORTEX_M55
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select ARMV8_M_DSP
select CPU_CORTEX_M_HAS_DWT
select ARMV8_1_M_PMU
select SOC_EARLY_INIT_HOOK
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select HAS_POWEROFF
config ARMV8_1_M_PMU_EVENTCNT
int
default 8 if SOC_SERIES_M55M1X
config SOC_M55M1XXX
select HAS_NUMAKER_HAL

9
soc/nuvoton/numaker/m55m1x/Kconfig.defconfig Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_M55M1X
rsource "Kconfig.defconfig.m55m1*"
endif # SOC_SERIES_M55M1X

10
soc/nuvoton/numaker/m55m1x/Kconfig.defconfig.m55m1xxx Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
if SOC_M55M1XXX
config NUM_IRQS
default 161
endif # SOC_M55M1XXX

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soc/nuvoton/numaker/m55m1x/Kconfig.soc Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_M55M1X
bool
select SOC_FAMILY_NUMAKER
help
Enable support for Nuvoton M55M1X MCU series
config SOC_M55M1XXX
bool
select SOC_SERIES_M55M1X
config SOC_SERIES
default "m55m1x" if SOC_SERIES_M55M1X
config SOC
default "m55m1xxx" if SOC_M55M1XXX

37
soc/nuvoton/numaker/m55m1x/mpu_regions.c Normal file
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/*
* Copyright (c) 2021 The Chromium OS Authors
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
MPU_REGION_ENTRY("SRAM",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
#if DT_NODE_EXISTS(DT_NODELABEL(itcm))
MPU_REGION_ENTRY("ITCM",
DT_REG_ADDR(DT_NODELABEL(itcm)),
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
DT_REG_SIZE(DT_NODELABEL(itcm)))),
#endif
#if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
MPU_REGION_ENTRY("DTCM",
DT_REG_ADDR(DT_NODELABEL(dtcm)),
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
DT_REG_SIZE(DT_NODELABEL(dtcm)))),
#endif
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

29
soc/nuvoton/numaker/m55m1x/poweroff.c Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/poweroff.h>
#include <NuMicro.h>
void z_sys_poweroff(void)
{
SYS_UnlockReg();
/* Select Power-down mode */
PMC_SetPowerDownMode(DT_PROP_OR(DT_NODELABEL(scc), powerdown_mode, PMC_SPD0),
PMC_PLCTL_PLSEL_PL0);
/* Clear all wake-up flag */
PMC->INTSTS |= PMC_INTSTS_CLRWK_Msk;
/* Enter to Power-down mode */
PMC_PowerDown();
k_cpu_idle();
CODE_UNREACHABLE;
}

18
soc/nuvoton/numaker/m55m1x/sections.ld Normal file
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/*
* Copyright (c) 2020 Mario Jaun
*
* SPDX-License-Identifier: Apache-2.0
*/
#if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
.dtcm_noinit (NOLOAD) : SUBALIGN(4)
{
__dtcm_noinit_start = .;
*(.dtcm_noinit)
*(".dtcm_noinit.*")
*(".kernel_noinit.*")
*(".noinit.*kernel/init.*")
*(".noinit.*kernel/mempool.*")
__dtcm_noinit_end = .;
} > DTCM
#endif

173
soc/nuvoton/numaker/m55m1x/soc.c Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
/* Hardware and starter kit includes. */
#include <NuMicro.h>
static void memory_setup(void)
{
/* Enable SRAM1/2 functions are only available in secure mode. */
if (SCU_IS_CPU_NS(SCU_NS) == 0) {
uint32_t wait_cnt;
/* To assign __HIRC value directly before BSS initialization. */
SystemCoreClock = __HIRC;
wait_cnt = SystemCoreClock;
/* Unlock protected registers */
do {
SYS->REGLCTL = 0x59UL;
SYS->REGLCTL = 0x16UL;
SYS->REGLCTL = 0x88UL;
} while (SYS->REGLCTL == 0UL);
/* Switch SRAM1 to normal power mode */
if (PMC->SYSRB1PC != 0) {
PMC->SYSRB1PC = 0;
}
/* Switch SRAM2 to normal power mode */
if (PMC->SYSRB2PC != 0) {
PMC->SYSRB2PC = 0;
}
/* Wait SRAM1/2 power mode change finish */
while (1) {
if ((PMC->SYSRB1PC & PMC_SYSRB1PC_PCBUSY_Msk) == 0 &&
(PMC->SYSRB2PC & PMC_SYSRB2PC_PCBUSY_Msk) == 0) {
break;
}
if (wait_cnt-- == 0) {
break;
}
}
/* Enable SRAM1/2 clock */
CLK->SRAMCTL |= (CLK_SRAMCTL_SRAM1CKEN_Msk | CLK_SRAMCTL_SRAM2CKEN_Msk);
}
#if (defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U))
/* Enable CP10 & CP11 Full Access */
SCB->CPACR |= ((3U << 10U * 2U) | (3U << 11U * 2U));
/* Set low-power state for PDEPU
* 0b00 | ON, PDEPU is not in low-power state
* 0b01 | ON, but the clock is off
* 0b10 | RET(ention)
* 0b11 | OFF
* Clear ELPSTATE, value is 0b11 on Cold reset
*/
PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk <<
PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos);
/* PDEPU ON with clock off, value is 0b01 */
PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
#endif
/* Enable only if configured to do so. */
SCB_InvalidateICache();
sys_cache_instr_enable();
/* Enable d-cache only if configured to do so. */
SCB_InvalidateDCache();
sys_cache_data_enable();
}
void soc_early_init_hook(void)
{
/* To ensure H/W I/O buffer with correct init data in SRAM,
* to clean D-Cache here to let all .bss & .data flush to SRAM.
*/
#ifdef CONFIG_DCACHE
SCB_CleanDCache();
#endif
SystemInit();
}
void soc_reset_hook(void)
{
memory_setup();
/* Unlock protected registers */
SYS_UnlockReg();
/* Release GPIO hold status */
PMC_RELEASE_GPIO();
/*
* -------------------
* Init System Clock
* -------------------
*/
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
/* Enable/disable 4~24 MHz external crystal oscillator (HXT) */
if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) {
CLK_EnableXtalRC(CLK_SRCCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) {
CLK_DisableXtalRC(CLK_SRCCTL_HXTEN_Msk);
}
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
/* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */
if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) {
CLK_EnableXtalRC(CLK_SRCCTL_LXTEN_Msk);
/* Wait for LXT clock ready */
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) {
CLK_DisableXtalRC(CLK_SRCCTL_LXTEN_Msk);
}
#endif
/* Enable 12 MHz high-speed internal RC oscillator (HIRC) */
CLK_EnableXtalRC(CLK_SRCCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Enable 32 KHz low-speed internal RC oscillator (LIRC) */
CLK_EnableXtalRC(CLK_SRCCTL_LIRCEN_Msk);
/* Wait for LIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
/* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
CLK_EnableXtalRC(CLK_SRCCTL_HIRC48MEN_Msk);
/* Wait for HIRC48 clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRC48MSTB_Msk);
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
CLK_DisableXtalRC(CLK_SRCCTL_HIRC48MEN_Msk);
}
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
/* Set CLK_PCLKDIV register on request */
CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv);
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
/* Set core clock (HCLK) on request */
CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock));
#endif
/*
* Update System Core Clock
* User can use SystemCoreClockUpdate() to calculate SystemCoreClock.
*/
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}

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soc/nuvoton/numaker/m55m1x/soc.h Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_
#define ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_
/* Hardware and starter kit includes. */
#include <NuMicro.h>
#endif /* ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_*/

3
soc/nuvoton/numaker/soc.yml
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@ -7,3 +7,6 @@ family:
- name: m2l31x
socs:
- name: m2l31xxx
- name: m55m1x
socs:
- name: m55m1xxx