From 47cc069cb9ef2024782eac9b2804b292ba30c8ef Mon Sep 17 00:00:00 2001 From: Lucien Zhao Date: Thu, 3 Oct 2024 23:19:01 +0800 Subject: [PATCH] drivers: clock_control: update mcux_lpc_syscon_clock.c drivers add more flexcomm instances clock support to adapt rt700 instances number add xspi clock support Signed-off-by: Lucien Zhao --- .../clock_control/clock_control_mcux_syscon.c | 67 ++++++++++++++++++- .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 18 ++++- 2 files changed, 80 insertions(+), 5 deletions(-) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 2fb8acd79eb..d26565b1a94 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -25,7 +25,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, #endif /* defined(CONFIG_CAN_MCUX_MCAN) */ #if defined(CONFIG_COUNTER_NXP_MRT) if ((uint32_t)sub_system == MCUX_MRT_CLK) { -#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) ||\ +#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) || \ defined(CONFIG_SOC_SERIES_MCXN) CLOCK_EnableClock(kCLOCK_Mrt); #elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT) @@ -242,14 +242,65 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de *rate = CLOCK_GetLPFlexCommClkFreq(9); break; + case MCUX_FLEXCOMM10_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(10); + break; + + case MCUX_FLEXCOMM11_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(11); + break; + + case MCUX_FLEXCOMM12_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(12); + break; + + case MCUX_FLEXCOMM13_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(13); + break; + + case MCUX_FLEXCOMM17_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(17); + break; + + case MCUX_FLEXCOMM18_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(18); + break; + + case MCUX_FLEXCOMM19_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(19); + break; + + case MCUX_FLEXCOMM20_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(20); + break; +#endif + + /* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */ +#if defined(CONFIG_SOC_SERIES_IMXRT7XX) && defined(CONFIG_SOC_FAMILY_NXP_IMXRT) + case MCUX_LPSPI14_CLK: + *rate = CLOCK_GetLPSpiClkFreq(14); + break; + case MCUX_LPI2C15_CLK: + *rate = CLOCK_GetLPI2cClkFreq(15); + break; + case MCUX_LPSPI16_CLK: + *rate = CLOCK_GetLPSpiClkFreq(16); + break; #endif #if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT) -#if CONFIG_SOC_SERIES_MCXN +#if defined(CONFIG_SOC_SERIES_MCXN) case MCUX_USDHC1_CLK: *rate = CLOCK_GetUsdhcClkFreq(); break; +#elif defined(CONFIG_SOC_SERIES_IMXRT7XX) + case MCUX_USDHC1_CLK: + *rate = CLOCK_GetUsdhcClkFreq(0); + break; + case MCUX_USDHC2_CLK: + *rate = CLOCK_GetUsdhcClkFreq(1); + break; #else case MCUX_USDHC1_CLK: *rate = CLOCK_GetSdioClkFreq(0); @@ -455,6 +506,18 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de *rate = CLOCK_GetLpi2cClkFreq(3); break; #endif /* defined(CONFIG_I2C_MCUX_LPI2C) */ + +#if defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED) + case MCUX_XSPI0_CLK: + *rate = CLOCK_GetXspiClkFreq(0); + break; + case MCUX_XSPI1_CLK: + *rate = CLOCK_GetXspiClkFreq(1); + break; + case MCUX_XSPI2_CLK: + *rate = CLOCK_GetXspiClkFreq(2); + break; +#endif /* defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED) */ } return 0; diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 77b5741b23d..32e0e228653 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -40,9 +40,16 @@ #define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK #define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) #define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) - -#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) -#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) +#define MCUX_FLEXCOMM17_CLK MCUX_LPC_CLK_ID(0x01, 0x11) +#define MCUX_FLEXCOMM18_CLK MCUX_LPC_CLK_ID(0x01, 0x12) +#define MCUX_FLEXCOMM19_CLK MCUX_LPC_CLK_ID(0x01, 0x13) +#define MCUX_FLEXCOMM20_CLK MCUX_LPC_CLK_ID(0x01, 0x14) +/* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */ +#define MCUX_LPSPI14_CLK MCUX_LPC_CLK_ID(0x01, 0x24) +#define MCUX_LPI2C15_CLK MCUX_LPC_CLK_ID(0x01, 0x25) +#define MCUX_LPSPI16_CLK MCUX_LPC_CLK_ID(0x01, 0x26) +#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) +#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) #define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) @@ -103,4 +110,9 @@ #define MCUX_LPI2C2_CLK MCUX_LPC_CLK_ID(0x14, 0x02) #define MCUX_LPI2C3_CLK MCUX_LPC_CLK_ID(0x14, 0x03) +#define MCUX_XSPI_CLK MCUX_LPC_CLK_ID(0x15, 0x00) +#define MCUX_XSPI0_CLK MCUX_LPC_CLK_ID(0x15, 0x00) +#define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x15, 0x01) +#define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x15, 0x02) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */