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boards: stm32: blackpill_f401ce: configure clocks using dt

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Migrate clock configuration for blackpill_f401ce board
from Kconfig to device tree.

Additionally, enable LSE crystal configuration for blackpill_f401ce.

Signed-off-by: Kalyan Sriram <kalyan@coderkalyan.com>
This commit is contained in:
Kalyan Sriram 2021-04-29 09:01:08 -07:00 • committed by Maureen Helm
commit 47961481ee
2 changed files with 22 additions and 17 deletions
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22
boards/arm/blackpill_f401ce/blackpill_f401ce.dts
View file

@ -115,3 +115,25 @@
pinctrl-0 = <&adc1_in1_pa1>;
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&pll {
div-m = <25>;
mul-n = <336>;
div-p = <4>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};

17
boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig
View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F401XE=y
# 84MHz system clock (highest value to get a precise USB clock should be 84MHz)
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -25,18 +23,3 @@ CONFIG_GPIO=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# HSE configuration
CONFIG_CLOCK_STM32_HSE_CLOCK=25000000
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# Produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=25
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
# Produce 42 MHz clock for USB
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1