arch: Moved atmel_sam3 to atmel_sam3x.

Found out that the SAM3 series is not a single series. There are actully
3 different series, 3U, 3A, and 3X.

Origin: Original
Jira: ZEP-2067

Change-Id: I61cdc826cc32dbdd25b5e6bafaada062c8ae8417
Signed-off-by: Justin Watson <jwatson5@gmail.com>
This commit is contained in:
fallrisk 2017-04-26 09:52:42 -07:00 committed by Kumar Gala
commit 4792f363a4
8 changed files with 34 additions and 34 deletions

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@ -1,4 +1,4 @@
# Kconfig - Atmel SAM3 MCU series configuration options # Kconfig - Atmel SAM3X MCU series configuration options
# #
# Copyright (c) 2017 Justin Watson # Copyright (c) 2017 Justin Watson
# Copyright (c) 2016 Intel Corporation. # Copyright (c) 2016 Intel Corporation.
@ -6,11 +6,11 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #
if SOC_SERIES_SAM3 || SOC_ATMEL_SAM3X8E if SOC_SERIES_SAM3X || SOC_ATMEL_SAM3X8E
config SOC_SERIES config SOC_SERIES
string string
default sam3 default sam3x
config SOC_PART_NUMBER config SOC_PART_NUMBER
string string
@ -49,7 +49,7 @@ config SRAM_BASE_ADDRESS
default 0x20070000 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E default 0x20070000 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E
# #
# Atmel SAM3 family has flash starting @ 0x00080000. # Atmel SAM3X family has flash starting @ 0x00080000.
# #
config FLASH_SIZE config FLASH_SIZE
default 512 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E default 512 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E
@ -104,4 +104,4 @@ config I2C_1_IRQ_PRI
endif # I2C endif # I2C
endif # SOC_SERIES_SAM3 endif # SOC_SERIES_SAM3X

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@ -1,4 +1,4 @@
# Kconfig - Atmel SAM3 MCU series # Kconfig - Atmel SAM3X MCU series
# #
# Copyright (c) 2017 Justin Watson # Copyright (c) 2017 Justin Watson
# Copyright (c) 2016 Intel Corporation. # Copyright (c) 2016 Intel Corporation.
@ -6,15 +6,15 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #
config SOC_SERIES_SAM3 config SOC_SERIES_SAM3X
bool "Atmel SAM3 MCU" bool "Atmel SAM3X MCU"
select CPU_CORTEX_M select CPU_CORTEX_M
select CPU_CORTEX_M3 select CPU_CORTEX_M3
select SOC_FAMILY_SAM select SOC_FAMILY_SAM
select SYS_POWER_LOW_POWER_STATE_SUPPORTED select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select CPU_HAS_SYSTICK select CPU_HAS_SYSTICK
help help
Enable support for Atmel SAM3 Cortex-M3 microcontrollers. Enable support for Atmel SAM3X Cortex-M3 microcontrollers.
Part No.: SAM3X8E Part No.: SAM3X8E
config SOC_ATMEL_SAM3X8E config SOC_ATMEL_SAM3X8E

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@ -1,4 +1,4 @@
# Kconfig - Atmel SAM3 MCU series # Kconfig - Atmel SAM3X MCU series
# #
# Copyright (c) 2017 Justin Watson # Copyright (c) 2017 Justin Watson
# Copyright (c) 2016 Intel Corporation. # Copyright (c) 2016 Intel Corporation.
@ -8,16 +8,16 @@
# #
choice choice
prompt "Atmel SAM3 MCU Selection" prompt "Atmel SAM3X MCU Selection"
depends on SOC_SERIES_SAM3 depends on SOC_SERIES_SAM3X
config SOC_PART_NUMBER_SAM3X8E config SOC_PART_NUMBER_SAM3X8E
bool "SAM3X8E" bool "SAM3X8E"
endchoice endchoice
if SOC_SERIES_SAM3 || SOC_ATMEL_SAM3X8E if SOC_SERIES_SAM3X || SOC_ATMEL_SAM3X8E
config SOC_ATMEL_SAM3_EXT_SLCK config SOC_ATMEL_SAM3X_EXT_SLCK
bool "Atmel SAM3 to use external crystal oscillator for slow clock" bool "Atmel SAM3 to use external crystal oscillator for slow clock"
default n default n
help help
@ -30,7 +30,7 @@ config SOC_ATMEL_SAM3_EXT_SLCK
The slow clock will be driven by the internal fast The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz. RC oscillator running at 32 kHz.
config SOC_ATMEL_SAM3_EXT_MAINCK config SOC_ATMEL_SAM3X_EXT_MAINCK
bool "Atmel SAM3 to use external crystal oscillator for main clock" bool "Atmel SAM3 to use external crystal oscillator for main clock"
default n default n
help help
@ -47,7 +47,7 @@ config SOC_ATMEL_SAM3_EXT_MAINCK
Says n here will use the internal fast RC oscillator Says n here will use the internal fast RC oscillator
running at 12 MHz. running at 12 MHz.
config SOC_ATMEL_SAM3_PLLA_MULA config SOC_ATMEL_SAM3X_PLLA_MULA
hex hex
default 0x06 default 0x06
help help
@ -60,7 +60,7 @@ config SOC_ATMEL_SAM3_PLLA_MULA
With default of MULA == 6, and DIVA == 1, With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock. PLL is running at 7 times of main clock.
config SOC_ATMEL_SAM3_PLLA_DIVA config SOC_ATMEL_SAM3X_PLLA_DIVA
hex hex
default 0x01 default 0x01
help help
@ -73,7 +73,7 @@ config SOC_ATMEL_SAM3_PLLA_DIVA
With default of MULA == 6, and DIVA == 1, With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock. PLL is running at 7 times of main clock.
config SOC_ATMEL_SAM3_WAIT_MODE config SOC_ATMEL_SAM3X_WAIT_MODE
bool "Atmel SAM3 goes to Wait mode instead of Sleep mode" bool "Atmel SAM3 goes to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAM3_EXT_MAINCK depends on SOC_ATMEL_SAM3_EXT_MAINCK
default y if DEBUG default y if DEBUG
@ -82,4 +82,4 @@ config SOC_ATMEL_SAM3_WAIT_MODE
to achieve this, make CPU go to Wait mode instead of Sleep to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock. mode while using external crystal oscillator for main clock.
endif # SOC_SERIES_SAM3 endif # SOC_SERIES_SAM3X

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@ -1,4 +1,4 @@
# Makefile - Atmel SAM3 MCU series # Makefile - Atmel SAM3X MCU series
# #
# Copyright (c) 2017 Justin Watson # Copyright (c) 2017 Justin Watson
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0

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@ -7,10 +7,10 @@
/** /**
* @file * @file
* @brief System/hardware module for Atmel SAM3 family processor * @brief System/hardware module for Atmel SAM3X series processor
* *
* This module provides routines to initialize and support board-level hardware * This module provides routines to initialize and support board-level hardware
* for the Atmel SAM3 family processor. * for the Atmel SAM3X series processor.
*/ */
#include <kernel.h> #include <kernel.h>
@ -39,7 +39,7 @@ static ALWAYS_INLINE void clock_init(void)
* (with reserved bits set to 0). * (with reserved bits set to 0).
*/ */
#ifdef CONFIG_SOC_ATMEL_SAM3_EXT_SLCK #ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK
/* This part is to switch the slow clock to using /* This part is to switch the slow clock to using
* the external 32 kHz crystal oscillator. * the external 32 kHz crystal oscillator.
*/ */
@ -52,7 +52,7 @@ static ALWAYS_INLINE void clock_init(void)
; ;
#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_SLCK */ #endif /* CONFIG_SOC_ATMEL_SAM3_EXT_SLCK */
#ifdef CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK #ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK
/* Start the external main oscillator */ /* Start the external main oscillator */
__PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ
| PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN
@ -72,7 +72,7 @@ static ALWAYS_INLINE void clock_init(void)
/* Wait for main oscillator to be selected */ /* Wait for main oscillator to be selected */
while (!(__PMC->sr & PMC_INT_MOSCSELS)) while (!(__PMC->sr & PMC_INT_MOSCSELS))
; ;
#ifdef CONFIG_SOC_ATMEL_SAM3_WAIT_MODE #ifdef CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE
/* /*
* Instruct CPU enter Wait mode instead of Sleep mode to * Instruct CPU enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug * keep Processor Clock (HCLK) and thus be able to debug
@ -139,7 +139,7 @@ static ALWAYS_INLINE void clock_init(void)
* *
* @return 0 * @return 0
*/ */
static int atmel_sam3_init(struct device *arg) static int atmel_sam3x_init(struct device *arg)
{ {
u32_t key; u32_t key;
@ -181,4 +181,4 @@ static int atmel_sam3_init(struct device *arg)
return 0; return 0;
} }
SYS_INIT(atmel_sam3_init, PRE_KERNEL_1, 0); SYS_INIT(atmel_sam3x_init, PRE_KERNEL_1, 0);

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@ -6,11 +6,11 @@
*/ */
/** /**
* @file SoC configuration macros for the Atmel SAM3 family processors. * @file SoC configuration macros for the Atmel SAM3X family processors.
*/ */
#ifndef _ATMEL_SAM3_SOC_H_ #ifndef _ATMEL_SAM3X_SOC_H_
#define _ATMEL_SAM3_SOC_H_ #define _ATMEL_SAM3X_SOC_H_
/* IRQ numbers (from section 9.1, Peripheral Identifiers). */ /* IRQ numbers (from section 9.1, Peripheral Identifiers). */
#define IRQ_SUPC 0 /* Supply Controller */ #define IRQ_SUPC 0 /* Supply Controller */
@ -131,9 +131,9 @@
* the processor clock is at 84 MHz. * the processor clock is at 84 MHz.
*/ */
#define PMC_CKGR_PLLAR_MULA \ #define PMC_CKGR_PLLAR_MULA \
((CONFIG_SOC_ATMEL_SAM3_PLLA_MULA) << 16) ((CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA) << 16)
#define PMC_CKGR_PLLAR_DIVA \ #define PMC_CKGR_PLLAR_DIVA \
((CONFIG_SOC_ATMEL_SAM3_PLLA_DIVA) << 0) ((CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA) << 0)
#define PMC_MCKR_CSS_MASK (0x3) #define PMC_MCKR_CSS_MASK (0x3)
#define PMC_MCKR_CSS_SLOW (0 << 0) #define PMC_MCKR_CSS_SLOW (0 << 0)
@ -244,4 +244,4 @@
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _ATMEL_SAM3_SOC_H_ */ #endif /* _ATMEL_SAM3X_SOC_H_ */

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@ -5,7 +5,7 @@
*/ */
/** /**
* @file SoC configuration macros for the Atmel SAM3 family processors. * @file SoC configuration macros for the Atmel SAM3X family processors.
* *
* Refer to the datasheet for more information about these registers. * Refer to the datasheet for more information about these registers.
*/ */