test: drivers: flash: build spi_nor.c wp & hold

Test spi_nor.c driver builds with or without wp-gpios and hold-gpios.

Signed-off-by: J.P. Hutchins <jp@intercreate.io>
This commit is contained in:
J.P. Hutchins 2023-05-31 14:04:20 -07:00 committed by Carles Cufí
commit 477ff70230
3 changed files with 134 additions and 0 deletions

View file

@ -0,0 +1,61 @@
/*
* Copyright (c) 2023 Intercreate, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Build test for jedec,spi-nor compatible (drivers/flash/spi_nor.c)
*/
/ {
aliases {
spi-flash0 = &mx25v1635fzui;
};
};
/delete-node/ &mx25r64;
&pinctrl {
spi0_default: spi0_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 9)>,
<NRF_PSEL(SPIM_MOSI, 0, 11)>,
<NRF_PSEL(SPIM_MISO, 0, 12)>;
};
};
spi0_sleep: spi0_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 9)>,
<NRF_PSEL(SPIM_MOSI, 0, 11)>,
<NRF_PSEL(SPIM_MISO, 0, 12)>;
low-power-enable;
};
};
};
&spi0 {
compatible = "nordic,nrf-spim";
status = "okay";
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; // mx25v16
pinctrl-0 = <&spi0_default>;
pinctrl-1 = <&spi0_sleep>;
pinctrl-names = "default", "sleep";
mx25v1635fzui: mx25v1635fzui@0 {
compatible = "jedec,spi-nor";
status = "okay";
reg = <0>;
spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
size = <0x1000000>; // bits
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <45000>;
jedec-id = [ C2 23 15 ];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f1 00 82 ec 04 c2 44 83 48 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
};
};

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@ -0,0 +1,63 @@
/*
* Copyright (c) 2023 Intercreate, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Build test for jedec,spi-nor compatible (drivers/flash/spi_nor.c) wp-gpios and hold-gpios
*/
/ {
aliases {
spi-flash0 = &mx25v1635fzui;
};
};
/delete-node/ &mx25r64;
&pinctrl {
spi0_default: spi0_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 9)>,
<NRF_PSEL(SPIM_MOSI, 0, 11)>,
<NRF_PSEL(SPIM_MISO, 0, 12)>;
};
};
spi0_sleep: spi0_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 9)>,
<NRF_PSEL(SPIM_MOSI, 0, 11)>,
<NRF_PSEL(SPIM_MISO, 0, 12)>;
low-power-enable;
};
};
};
&spi0 {
compatible = "nordic,nrf-spim";
status = "okay";
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; // mx25v16
pinctrl-0 = <&spi0_default>;
pinctrl-1 = <&spi0_sleep>;
pinctrl-names = "default", "sleep";
mx25v1635fzui: mx25v1635fzui@0 {
compatible = "jedec,spi-nor";
status = "okay";
reg = <0>;
spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
size = <0x1000000>; // bits
hold-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <45000>;
jedec-id = [ C2 23 15 ];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f1 00 82 ec 04 c2 44 83 48 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
};
};

View file

@ -79,3 +79,13 @@ tests:
platform_allow: mr_canhubk3
extra_configs:
- CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME=y
drivers.flash.common.spi_nor:
platform_allow: nrf52840dk_nrf52840
extra_args:
- OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf
- DTC_OVERLAY_FILE=boards/nrf52840dk_spi_nor.overlay
drivers.flash.common.spi_nor_wp_hold:
platform_allow: nrf52840dk_nrf52840
extra_args:
- OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf
- DTC_OVERLAY_FILE=boards/nrf52840dk_spi_nor_wp_hold.overlay