include: arm64: Add mpu data struct definition
According to Armv8-R64 Spec, MPU related meta data(region base/limit) is 64 bits. So we need to re-define MPU related data structure here. Signed-off-by: Haibo Xu <haibo.xu@arm.com> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This commit is contained in:
Jaxson Han
Anas Nashif
parent
72287491df
commit
475374ce2f
3 changed files with 248 additions and 0 deletions
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@ -418,6 +418,7 @@
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/include/arch/arm/aarch32/ @MaureenHelm @galak @ioannisg
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/include/arch/arm/aarch32/cortex_a_r/ @stephanosio
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/include/arch/arm64/ @carlocaione
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/include/arch/arm64/cortex_r/ @povergoing
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/include/arch/arm/aarch32/irq.h @carlocaione
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/include/arch/nios2/ @nashif
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/include/arch/nios2/arch.h @nashif
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233
include/arch/arm64/cortex_r/mpu/arm_mpu.h
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include/arch/arm64/cortex_r/mpu/arm_mpu.h
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@ -0,0 +1,233 @@
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/*
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* Copyright (c) 2018 Linaro Limited.
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* Copyright (c) 2018 Nordic Semiconductor ASA.
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* Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
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#ifndef _ASMLANGUAGE
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/*
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* Convenience macros to represent the ARMv8-R64-specific configuration
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* for memory access permission and cache-ability attribution.
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*/
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/* MPU MPUIR Register Definitions */
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#define MPU_IR_REGION_Msk (0xFFU)
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/* MPU RBAR Register attribute msk Definitions */
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#define MPU_RBAR_BASE_Pos 6U
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#define MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
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#define MPU_RBAR_SH_Pos 4U
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#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
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#define MPU_RBAR_AP_Pos 2U
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#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
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/* RBAR_EL1 XN */
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#define MPU_RBAR_XN_Pos 1U
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#define MPU_RBAR_XN_Msk (0x1UL << MPU_RBAR_XN_Pos)
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/* MPU PLBAR_ELx Register Definitions */
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#define MPU_RLAR_LIMIT_Pos 6U
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#define MPU_RLAR_LIMIT_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
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#define MPU_RLAR_AttrIndx_Pos 1U
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#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
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#define MPU_RLAR_EN_Msk (0x1UL)
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/* PRBAR_ELx: Attribute flag for not-allowing execution (eXecute Never) */
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#define NOT_EXEC MPU_RBAR_XN_Msk /* PRBAR_EL1 */
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/* PRBAR_ELx: Attribute flag for access permissions */
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/* Privileged Read Write, Unprivileged No Access */
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#define P_RW_U_NA 0x0U
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#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
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/* Privileged Read Write, Unprivileged Read Write */
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#define P_RW_U_RW 0x1U
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#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
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/* Privileged Read Only, Unprivileged No Access */
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#define P_RO_U_NA 0x2U
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#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
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/* Privileged Read Only, Unprivileged Read Only */
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#define P_RO_U_RO 0x3U
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#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
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/* PRBAR_ELx: Attribute flags for share-ability */
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#define NON_SHAREABLE 0x0U
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#define NON_SHAREABLE_Msk \
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((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
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#define OUTER_SHAREABLE 0x2U
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#define OUTER_SHAREABLE_Msk \
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((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
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#define INNER_SHAREABLE 0x3U
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#define INNER_SHAREABLE_Msk \
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((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
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/* MPIR_ELx Attribute flags for cache-ability */
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/* Memory Attributes for Device Memory
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* 1.Gathering (G/nG)
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* Determines whether multiple accesses can be merged into a single
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* bus transaction.
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* nG: Number/size of accesses on the bus = number/size of accesses
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* in code.
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*
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* 2.Reordering (R/nR)
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* Determines whether accesses to the same device can be reordered.
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* nR: Accesses to the same IMPLEMENTATION DEFINED block size will
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* appear on the bus in program order.
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*
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* 3 Early Write Acknowledgment (E/nE)
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* Indicates to the memory system whether a buffer can send
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* acknowledgements.
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* nE: The response should come from the end slave, not buffering in
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* the interconnect.
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*/
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#define DEVICE_nGnRnE 0x0U
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#define DEVICE_nGnRE 0x4U
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#define DEVICE_nGRE 0x8U
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#define DEVICE_GRE 0xCU
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/* Read/Write Allocation Configurations for Cacheable Memory */
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#define R_NON_W_NON 0x0U /* Do not allocate Read/Write */
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#define R_NON_W_ALLOC 0x1U /* Do not allocate Read, Allocate Write */
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#define R_ALLOC_W_NON 0x2U /* Allocate Read, Do not allocate Write */
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#define R_ALLOC_W_ALLOC 0x3U /* Allocate Read/Write */
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/* Memory Attributes for Normal Memory */
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#define NORMAL_O_WT_NT 0x80U /* Normal, Outer Write-through non-transient */
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#define NORMAL_O_WB_NT 0xC0U /* Normal, Outer Write-back non-transient */
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#define NORMAL_O_NON_C 0x40U /* Normal, Outer Non-Cacheable */
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#define NORMAL_I_WT_NT 0x08U /* Normal, Inner Write-through non-transient */
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#define NORMAL_I_WB_NT 0x0CU /* Normal, Inner Write-back non-transient */
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#define NORMAL_I_NON_C 0x04U /* Normal, Inner Non-Cacheable */
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/* Global MAIR configurations */
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#define MPU_MAIR_INDEX_DEVICE 0U
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#define MPU_MAIR_ATTR_DEVICE (DEVICE_nGnRnE)
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#define MPU_MAIR_INDEX_FLASH 1U
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#define MPU_MAIR_ATTR_FLASH \
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((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) | \
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(NORMAL_I_WT_NT | R_ALLOC_W_NON))
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#define MPU_MAIR_INDEX_SRAM 2U
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#define MPU_MAIR_ATTR_SRAM \
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((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) | \
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(NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
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#define MPU_MAIR_INDEX_SRAM_NOCACHE 3U
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#define MPU_MAIR_ATTR_SRAM_NOCACHE \
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((NORMAL_O_NON_C | (R_NON_W_NON << 4)) | \
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(NORMAL_I_NON_C | R_NON_W_NON))
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#define MPU_MAIR_ATTRS \
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((MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)) | \
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(MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) | \
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(MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) | \
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(MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)))
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/* Some helper defines for common regions.
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*
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* Note that the ARMv8-R MPU architecture requires that the
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* enabled MPU regions are non-overlapping. Therefore, it is
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* recommended to use these helper defines only for configuring
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* fixed MPU regions at build-time.
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*/
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#define REGION_DEVICE_ATTR \
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{ \
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/* AP, XN, SH */ \
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.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_DEVICE, \
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}
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#define REGION_RAM_ATTR \
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{ \
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/* AP, XN, SH */ \
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.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_SRAM, \
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}
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#define REGION_RAM_TEXT_ATTR \
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{ \
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/* AP, XN, SH */ \
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.rbar = P_RO_U_NA_Msk | NON_SHAREABLE_Msk, \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_SRAM, \
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}
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#define REGION_RAM_RO_ATTR \
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{ \
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/* AP, XN, SH */ \
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.rbar = NOT_EXEC | P_RO_U_NA_Msk | NON_SHAREABLE_Msk, \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_SRAM, \
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}
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#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
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/* Note that the access permissions allow for un-privileged writes
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*/
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#define REGION_FLASH_ATTR \
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{ \
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.rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_FLASH, \
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}
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#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
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#define REGION_FLASH_ATTR \
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{ \
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.rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_FLASH, \
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}
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#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
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struct arm_mpu_region_attr {
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/* Attributes belonging to PRBAR */
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uint8_t rbar : 5;
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/* MAIR index for attribute indirection */
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uint8_t mair_idx : 3;
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};
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/* Region definition data structure */
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struct arm_mpu_region {
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/* Region Base Address */
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uint64_t base;
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/* Region limit Address */
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uint64_t limit;
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/* Region Name */
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const char *name;
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/* Region Attributes */
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struct arm_mpu_region_attr attr;
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};
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/* MPU configuration data structure */
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struct arm_mpu_config {
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/* Number of regions */
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uint32_t num_regions;
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/* Regions */
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const struct arm_mpu_region *mpu_regions;
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};
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#define MPU_REGION_ENTRY(_name, _base, _limit, _attr) \
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{ \
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.name = _name, \
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.base = _base, \
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.limit = _limit, \
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.attr = _attr, \
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}
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/* Reference to the MPU configuration.
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*
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* This struct is defined and populated for each SoC (in the SoC definition),
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* and holds the build-time configuration information for the fixed MPU
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* regions enabled during kernel initialization. Dynamic MPU regions (e.g.
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* for Thread Stack, Stack Guards, etc.) are programmed during runtime, thus,
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* not kept here.
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*/
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extern const struct arm_mpu_config mpu_config;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_ */
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@ -64,6 +64,7 @@ MAKE_REG_HELPER(currentel);
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MAKE_REG_HELPER(daif)
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MAKE_REG_HELPER(hcr_el2);
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MAKE_REG_HELPER(id_aa64pfr0_el1);
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MAKE_REG_HELPER(id_aa64mmfr0_el1);
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MAKE_REG_HELPER(scr_el3);
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MAKE_REG_HELPER_EL123(actlr)
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@ -79,6 +80,19 @@ MAKE_REG_HELPER_EL123(tcr)
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MAKE_REG_HELPER_EL123(ttbr0)
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MAKE_REG_HELPER_EL123(vbar)
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#if defined(CONFIG_ARM_MPU)
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/* Armv8-R aarch64 mpu registers */
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#define mpuir_el1 S3_0_c0_c0_4
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#define prselr_el1 S3_0_c6_c2_1
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#define prbar_el1 S3_0_c6_c8_0
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#define prlar_el1 S3_0_c6_c8_1
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MAKE_REG_HELPER(mpuir_el1);
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MAKE_REG_HELPER(prselr_el1);
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MAKE_REG_HELPER(prbar_el1);
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MAKE_REG_HELPER(prlar_el1);
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#endif
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static ALWAYS_INLINE void enable_debug_exceptions(void)
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{
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__asm__ volatile ("msr DAIFClr, %0"
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