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arch: sparc: fix memory barrier behavior of arch_irq_*lock

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Correct functioning of spinlocks requires that they be memory barriers.
Most architectures achieve this by using the GCC extended asm syntax to
force a compiler soft barrier at the point the interrupt status is
changing.  This clobber was missing from the SPARC definition, so add
it.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit is contained in:
Peter Bigot 2021-01-26 09:46:04 -06:00 • committed by Anas Nashif
commit 4720585077
1 changed files with 2 additions and 1 deletions
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3
include/arch/sparc/arch.h
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@ -66,7 +66,8 @@ static ALWAYS_INLINE unsigned int z_sparc_set_pil_inline(unsigned int newpil)
__asm__ volatile (
"ta %1\nnop\n" :
"=r" (oldpil) :
"i" (SPARC_SW_TRAP_SET_PIL), "r" (oldpil)
"i" (SPARC_SW_TRAP_SET_PIL), "r" (oldpil) :
"memory"
);
return oldpil;
}