soc/riscv: it8xxx2 soc system

A new platform soc for it8xxx2.
Revising the test/kernel/context/src/main.c for it8xxx2 test case.

Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>

soc/riscv/riscv-ite/CMakeLists.txt

@@ -0,0 +1,3 @@
+add_subdirectory(common)
+add_subdirectory(${SOC_SERIES})
+zephyr_compile_options(-march=rv32i)

soc/riscv/riscv-ite/Kconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_RISCV_ITE
+	bool
+	help
+	  omit prompt to signify a "hidden" option
+
+config SOC_FAMILY
+	string
+	default "riscv-ite"
+	depends on SOC_FAMILY_RISCV_ITE
+
+source "soc/riscv/riscv-ite/*/Kconfig.soc"

soc/riscv/riscv-ite/Kconfig.defconfig

@@ -0,0 +1,4 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/riscv/riscv-ite/*/Kconfig.defconfig.series"

soc/riscv/riscv-ite/Kconfig.soc

@@ -0,0 +1,4 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/riscv/riscv-ite/*/Kconfig.series"

soc/riscv/riscv-ite/common/CMakeLists.txt

@@ -0,0 +1,7 @@
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc_irq.S
+  soc_common_irq.c
+  vector.S
+  )

soc/riscv/riscv-ite/common/encoding.h

@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_HPP         0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_PUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_VM          0x1F000000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS64_SD        0x8000000000000000
+
+
+#define MCAUSE32_CAUSE       0x7FFFFFFF
+#define MCAUSE64_CAUSE       0x7FFFFFFFFFFFFFFF
+#define MCAUSE32_INT         0x80000000
+#define MCAUSE64_INT         0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_PUM         0x00040000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB   1
+#define VM_MBBID 2
+#define VM_SV32  8
+#define VM_SV39  9
+#define VM_SV48  10
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define DEFAULT_NMIVEC     0x00001004
+#define DEFAULT_MTVEC      0x00001010
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define MCAUSE_INT MCAUSE64_INT
+# define MCAUSE_CAUSE MCAUSE64_CAUSE
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define MCAUSE_INT MCAUSE32_INT
+# define MCAUSE_CAUSE MCAUSE32_CAUSE
+#endif /* __riscv64 */
+
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#endif

soc/riscv/riscv-ite/common/soc_common.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file configuration macros for riscv SOCs supporting the riscv
+ *       privileged architecture specification
+ */
+
+#ifndef __SOC_COMMON_H_
+#define __SOC_COMMON_H_
+
+#include "chip_chipregs.h"
+#include "encoding.h"
+
+/* IRQ numbers */
+#define RISCV_MACHINE_SOFT_IRQ       161  /* Machine Software Interrupt */
+#define RISCV_MACHINE_TIMER_IRQ      157  /* Machine Timer Interrupt */
+#define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
+
+#define RISCV_MAX_GENERIC_IRQ        191 /* Max Generic Interrupt */
+
+/* Exception numbers */
+#define RISCV_MACHINE_ECALL_EXP      11 /* Machine ECALL instruction */
+
+/*
+ * SOC-specific MSTATUS related info
+ */
+/* MSTATUS register to save/restore upon interrupt/exception/context switch */
+#define SOC_MSTATUS_REG              mstatus
+
+#define SOC_MSTATUS_IEN              (1 << 3) /* Machine Interrupt Enable bit */
+
+/* Previous Privilege Mode - Machine Mode */
+#define SOC_MSTATUS_MPP_M_MODE       (3 << 11)
+/* Interrupt Enable Bit in Previous Privilege Mode */
+#define SOC_MSTATUS_MPIE             (1 << 7)
+
+/*
+ * Default MSTATUS register value to restore from stack
+ * upon scheduling a thread for the first time
+ */
+#define SOC_MSTATUS_DEF_RESTORE      (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE)
+
+
+/* SOC-specific MCAUSE bitfields */
+/* Interrupt Mask */
+#define SOC_MCAUSE_IRQ_MASK          (1 << 31)
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
+/* ECALL exception number */
+#define SOC_MCAUSE_ECALL_EXP         RISCV_MACHINE_ECALL_EXP
+
+/* SOC-Specific EXIT ISR command */
+#define SOC_ERET                     mret
+
+#ifndef _ASMLANGUAGE
+
+#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
+void soc_interrupt_init(void);
+#endif
+
+#if defined(CONFIG_RISCV_HAS_PLIC)
+void riscv_plic_irq_enable(u32_t irq);
+void riscv_plic_irq_disable(u32_t irq);
+int riscv_plic_irq_is_enabled(u32_t irq);
+void riscv_plic_set_priority(u32_t irq, u32_t priority);
+int riscv_plic_get_irq(void);
+#endif
+
+#if CONFIG_ITE_IT8XXX2_INTC
+extern void ite_intc_irq_enable(unsigned int irq);
+extern void ite_intc_irq_disable(unsigned int irq);
+extern int ite_intc_irq_is_enable(unsigned int irq);
+extern void ite_intc_irq_priority_set(unsigned int irq,
+			unsigned int prio, unsigned int flags);
+#endif /* CONFIG_ITE_IT8XXX2_INTC */
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* __SOC_COMMON_H_ */

soc/riscv/riscv-ite/common/soc_common_irq.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief interrupt management code for riscv SOCs supporting the riscv
+	  privileged architecture specification
+ */
+#include <irq.h>
+
+void arch_irq_enable(unsigned int irq)
+{
+#if CONFIG_ITE_IT8XXX2_INTC
+	if (irq > 0) {
+		ite_intc_irq_enable(irq);
+	}
+#else
+	uint32_t mie;
+
+#if defined(CONFIG_RISCV_HAS_PLIC)
+	if (irq > RISCV_MAX_GENERIC_IRQ) {
+		riscv_plic_irq_enable(irq);
+		return;
+	}
+#endif
+
+	/*
+	 * CSR mie register is updated using atomic instruction csrrs
+	 * (atomic read and set bits in CSR register)
+	 */
+	__asm__ volatile ("csrrs %0, mie, %1\n"
+			  : "=r" (mie)
+			  : "r" (1 << irq));
+#endif /* CONFIG_ITE_IT8XXX2_INTC */
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+#if CONFIG_ITE_IT8XXX2_INTC
+	if (irq > 0) {
+		ite_intc_irq_disable(irq);
+	}
+#else
+	uint32_t mie;
+
+#if defined(CONFIG_RISCV_HAS_PLIC)
+	if (irq > RISCV_MAX_GENERIC_IRQ) {
+		riscv_plic_irq_disable(irq);
+		return;
+	}
+#endif
+
+	/*
+	 * Use atomic instruction csrrc to disable device interrupt in mie CSR.
+	 * (atomic read and clear bits in CSR register)
+	 */
+	__asm__ volatile ("csrrc %0, mie, %1\n"
+			  : "=r" (mie)
+			  : "r" (1 << irq));
+#endif /* CONFIG_ITE_IT8XXX2_INTC */
+};
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	uint32_t mie;
+
+#if defined(CONFIG_RISCV_HAS_PLIC)
+	if (irq > RISCV_MAX_GENERIC_IRQ)
+		return riscv_plic_irq_is_enabled(irq);
+#endif
+
+	__asm__ volatile ("csrr %0, mie" : "=r" (mie));
+
+#if CONFIG_ITE_IT8XXX2_INTC
+	return (mie && (ite_intc_irq_is_enable(irq)));
+#else
+	return !!(mie & (1 << irq));
+#endif /* CONFIG_ITE_IT8XXX2_INTC */
+}
+
+#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
+void soc_interrupt_init(void)
+{
+	/* ensure that all interrupts are disabled */
+	(void)irq_lock();
+
+	__asm__ volatile ("csrwi mie, 0\n"
+			  "csrwi mip, 0\n");
+}
+#endif

soc/riscv/riscv-ite/common/soc_irq.S

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * common interrupt management code for riscv SOCs supporting the riscv
+ * privileged architecture specification
+ */
+#include <kernel_structs.h>
+#include <offsets.h>
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <soc.h>
+
+/* exports */
+GTEXT(__soc_handle_irq)
+
+/*
+ * SOC-specific function to handle pending IRQ number generating the interrupt.
+ * Exception number is given as parameter via register a0.
+ */
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	/* Clear exception number from CSR mip register */
+	li t1, 1
+	sll t0, t1, a0
+	csrrc t1, mip, t0
+	move t2,ra
+	call    get_irq
+	move ra,t2
+
+	/* Return */
+	jalr x0, ra
+
+/*
+ * __soc_is_irq is defined as .weak to allow re-implementation by
+ * SOCs that does not truely follow the riscv privilege specification.
+ */
+WTEXT(__soc_is_irq)
+
+/*
+ * SOC-specific function to determine if the exception is the result of a
+ * an interrupt or an exception
+ * return 1 (interrupt) or 0 (exception)
+ *
+ */
+SECTION_FUNC(exception.other, __soc_is_irq)
+	/* Read mcause and check if interrupt bit is set */
+	csrr t0, mcause
+	li t1, SOC_MCAUSE_IRQ_MASK
+	and t0, t0, t1
+
+	/* If interrupt bit is not set, return with 0 */
+	addi a0, x0, 0
+	beqz t0, not_interrupt
+	addi a0, a0, 1
+
+not_interrupt:
+	/* return */
+	jalr x0, ra

soc/riscv/riscv-ite/common/vector.S

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ * Jyunlin Chen <jyunlin.chen@ite.com.tw>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <toolchain.h>
+
+/* exports */
+GTEXT(__start)
+
+/* imports */
+GTEXT(__initialize)
+GTEXT(__irq_wrapper)
+
+SECTION_FUNC(vectors, __start)
+	.option norvc;
+
+	/*
+	 * Set mtvec (Machine Trap-Vector Base-Address Register)
+	 * to __irq_wrapper.
+	 */
+	la t0, __irq_wrapper
+	csrw mtvec, t0
+	csrwi mie, 0
+
+	/* Jump to __initialize */
+	tail __initialize
+
+/**
+ *-----------------------------------------------------------------------------
+ * 16-bytes signature
+ *-----------------------------------------------------------------------------
+ */
+    .org 0x84
+                ## 0    1    2    3    4    5    6                     7
+    .byte       0xA5,0xA5,0xA5,0xA5,0xA5,0xA5,0xA5,0xB5
+                ## 8    9   10   11   12                    13   14   15
+    .byte       0x85,0x12,0x5A,0x5A,0xAA,0xAA,0x55,0x55
+/**
+ *-----------------------------------------------------------------------------
+ * EC firmware version
+ *-----------------------------------------------------------------------------
+ */
+
+    .byte  'I', 'T', '8', 'X', 'X', 'X', '2', '-', 'A', 'X', '-',\
+	'V', '0', '.', '0', '0'
+    .org 0xa4

soc/riscv/riscv-ite/it8xxx2/CMakeLists.txt

@@ -0,0 +1,3 @@
+zephyr_sources(
+	soc.c
+)

soc/riscv/riscv-ite/it8xxx2/Kconfig.defconfig.series

@@ -0,0 +1,37 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RISCV32_IT8XXX2
+
+config SOC_SERIES
+	default "it8xxx2"
+
+config ITE_IT8XXX2_INTC
+	default y
+	select FLASH
+	select FLASH_HAS_PAGE_LAYOUT
+	select FLASH_HAS_DRIVER_ENABLED
+	select HAS_FLASH_LOAD_OFFSET
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 660000
+
+if ITE_IT8XXX2_INTC
+config NUM_IRQS
+	default 162
+
+config DYNAMIC_INTERRUPTS
+	default y
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_START_VECTOR
+	default 0
+
+config GEN_SW_ISR_TABLE
+	default y
+
+endif # ITE_IT8XXX2_INTC
+
+endif # SOC_SERIES_RISCV32_IT8XXX2

soc/riscv/riscv-ite/it8xxx2/Kconfig.series

@@ -0,0 +1,9 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RISCV32_IT8XXX2
+	bool "ITE IT8XXX2 implementation"
+	#depends on RISCV
+	select SOC_FAMILY_RISCV_ITE
+	help
+	    Enable support for ITE IT8XXX2

soc/riscv/riscv-ite/it8xxx2/Kconfig.soc

@@ -0,0 +1,13 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+prompt "ITE IT8XXX2 system implementation"
+depends on SOC_SERIES_RISCV32_IT8XXX2
+
+config SOC_IT8XXX2
+	bool "ITE IT8XXX2 system implementation"
+	select RISCV
+	select ATOMIC_OPERATIONS_C
+
+endchoice

soc/riscv/riscv-ite/it8xxx2/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/riscv/common/linker.ld>

soc/riscv/riscv-ite/it8xxx2/soc.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+void sys_arch_reboot(int type)
+{
+	ARG_UNUSED(type);
+}
+
+static int ite_it8xxx2_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
+	/* uart1 board init */
+	CGCTRL3R &= ~(BIT(2));
+	AUTOCG &= ~(BIT(6));
+	RSTDMMC |= BIT(3);	/* Set EC side control */
+	RSTC4 = BIT(1);	/* W-One to reset controller */
+	GPCRB0 = 0x00;		/* tx pin init */
+	GPCRB1 = 0x00;		/* rx pin init */
+	GPCRF3 = 0x00;		/* rts pin init */
+	GPCRD5 = 0x00;		/* cts pin init */
+#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
+	/* uart2 board init */
+	GCR21 &= ~(BIT(0) | BIT(1));	/* setting voltage 3.3v */
+	CGCTRL3R &= ~(BIT(2));
+	AUTOCG &= ~(BIT(5));
+	RSTDMMC |= BIT(2);	/* Set EC side control */
+	RSTC4 = BIT(2);	/* W-One to reset controller */
+	GPCRH1 = 0x00;		/* tx pin init */
+	GPCRH2 = 0x00;		/* rx pin init */
+	GPCRE5 = 0x00;		/* rts pin init */
+	GPCRI7 = 0x00;		/* cts pin init */
+#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
+	return 0;
+}
+SYS_INIT(ite_it8xxx2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/riscv/riscv-ite/it8xxx2/soc.h

@@ -0,0 +1,28 @@
+#ifndef __RISCV_ITE_SOC_H_
+#define __RISCV_ITE_SOC_H_
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+#include <soc_common.h>
+#include <devicetree.h>
+
+#define UART_REG_ADDR_INTERVAL 1
+
+/* lib-c hooks required RAM defined variables */
+#define RISCV_RAM_BASE               CONFIG_SRAM_BASE_ADDRESS
+#define RISCV_RAM_SIZE               KB(CONFIG_SRAM_SIZE)
+
+#define ite_write(reg, reg_size, val) \
+			((*((volatile unsigned char *)(reg))) = val)
+#define ite_read(reg, reg_size) \
+			(*((volatile unsigned char *)(reg)))
+
+/* PINMUX config */
+#define IT8XXX2_PINMUX_IOF0		0x00
+#define IT8XXX2_PINMUX_IOF1		0x01
+#define IT8XXX2_PINMUX_PINS		128
+
+#endif /* __RISCV_ITE_SOC_H_ */

tests/kernel/context/src/main.c

@@ -67,6 +67,8 @@
 #define TICK_IRQ IRQ_TIMER0
 #elif defined(CONFIG_RISCV_MACHINE_TIMER)
 #define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
+#elif defined(CONFIG_ITE_IT8XXX2_TIMER)
+#define TICK_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq)
 #elif defined(CONFIG_LITEX_TIMER)
 #define TICK_IRQ DT_IRQN(DT_NODELABEL(timer0))
 #elif defined(CONFIG_RV32M1_LPTMR_TIMER)