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boards: arm: pinnacle_100_dvk: Update clock error

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The 32KHz crystal used is a tuning fork crystal which can have a larger
clock drift over temperature than an AT cut crystal, therefore the LFXO
clock source error rate needs updating to account for this possible
drift over temperature.

Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
This commit is contained in:
Jamie McCrae 2021-08-06 09:49:48 +01:00 • committed by Kumar Gala
commit 46d6b8f528
1 changed files with 9 additions and 5 deletions
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14
boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig
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@ -1,4 +1,4 @@
# Copyright (c) 2020 Laird Connectivity
# Copyright (c) 2020-2021 Laird Connectivity
# SPDX-License-Identifier: Apache-2.0
@ -12,15 +12,19 @@ CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# enable GPIO
# Enable GPIO
CONFIG_GPIO=y
# enable uart driver
# Enable uart driver
CONFIG_SERIAL=y
# enable console
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# additional board options
# Additional board options
CONFIG_GPIO_AS_PINRESET=y
# 32KHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y