pwm: Remove k64-specific driver and k20_sim.h
Now that we have an mcux shim driver, remove the old k64-specific driver. Also remove include/drivers/k20_sim.h, since the old k64-specific driver was the only thing left using it. Jira: ZEP-2025 Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm
Anas Nashif
parent
57bd281d4d
commit
469ddab780
9 changed files with 0 additions and 1840 deletions
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@ -127,14 +127,6 @@ extern "C" {
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#include <misc/util.h>
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#include <misc/util.h>
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#include <drivers/rand32.h>
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#include <drivers/rand32.h>
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/*
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* PWM/FTM configuration settings
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*/
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#define PWM_K64_FTM_0_REG_BASE 0x40038000
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#define PWM_K64_FTM_1_REG_BASE 0x40039000
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#define PWM_K64_FTM_2_REG_BASE 0x4003A000
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#define PWM_K64_FTM_3_REG_BASE 0x400B9000
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#endif /* !_ASMLANGUAGE */
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -117,13 +117,6 @@ config FXOS8700_GPIO_PIN
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endif # FXOS8700
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endif # FXOS8700
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if PWM_K64_FTM
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config PWM_K64_FTM_0
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def_bool y
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endif # PWM_K64_FTM
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if PWM_MCUX_FTM
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if PWM_MCUX_FTM
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config PWM_3
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config PWM_3
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@ -130,13 +130,6 @@ config FXAS21002_GPIO_PIN
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endif # FXAS21002
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endif # FXAS21002
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if PWM_K64_FTM
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config PWM_K64_FTM_0
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def_bool y
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endif # PWM_K64_FTM
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if PWM_MCUX_FTM
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if PWM_MCUX_FTM
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config PWM_3
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config PWM_3
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@ -51,8 +51,6 @@ source "drivers/pwm/Kconfig.qmsi"
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source "drivers/pwm/Kconfig.dw"
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source "drivers/pwm/Kconfig.dw"
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source "drivers/pwm/Kconfig.k64"
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source "drivers/pwm/Kconfig.stm32"
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source "drivers/pwm/Kconfig.stm32"
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source "drivers/pwm/Kconfig.nrf5_sw"
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source "drivers/pwm/Kconfig.nrf5_sw"
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@ -1,480 +0,0 @@
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# Kconfig.k64 - K64_FTM PWM configuration options
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#
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#
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# Copyright (c) 2016 Intel Corporation
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# Copyright (c) 2016 Wind River Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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################################################
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# K64 Flex Timer Module (FTM)
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################################################
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menuconfig PWM_K64_FTM
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bool "PWM with Freescale K64 Flex Timer Module (FTM)"
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depends on PWM && SOC_MK64F12
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default n
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help
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Enable Pulse Width Modulation driver for Freescale
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K64 Flex Timer Module (FTM).
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if PWM_K64_FTM
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config SYS_LOG_PWM_K64_FTM_LEVEL
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int
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prompt "Sets log level for pwm_ftm driver"
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depends on PWM_K64_FTM && SYS_LOG
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default 0
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help
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Sets log level for pwm_ftm driver.
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Levels are:
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- 0 OFF, do not write
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- 1 ERROR, only write SYS_LOG_ERR
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- 2 WARNING, write SYS_LOG_WRN in addition to previous level
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- 3 INFO, write SYS_LOG_INF in addition to previous levels
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- 4 DEBUG, write SYS_LOG_DBG in addition to previous levels
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#### FTM0 #####
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config PWM_K64_FTM_0
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bool "K64 FTM PWM Module 0"
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depends on PWM_K64_FTM
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default n
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help
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Enable config PWM options for FTM0 source module.
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config PWM_K64_FTM_0_DEV_NAME
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string "K64 FTM PWM Module 0 Device Name"
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depends on PWM_K64_FTM_0
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default "PWM_0"
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help
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Specify the device name for the FTM0 source module.
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config PWM_K64_FTM_0_PRESCALE
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int "K64 FTM0 prescale value"
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default 1
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depends on PWM_K64_FTM_0
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help
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Specify the FTM timer prescale value. The valid values are
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1, 2, 4, 8, 16, 32, 64, or 128.
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config PWM_K64_FTM_0_PERIOD
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int "K64 FTM0 period value"
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default 65535
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depends on PWM_K64_FTM_0
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help
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Specify the FTM0 PWM period in ticks
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menu "K64 FTM0 Clock Source"
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depends on PWM_K64_FTM_0
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choice PWM_K64_FTM_0_CLOCK_SOURCE_CHOICE
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prompt "Choose the K64 FTM0 clock source"
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default PWM_K64_FTM_0_CLOCK_SOURCE_SYSTEM
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config PWM_K64_FTM_0_CLOCK_SOURCE_NONE
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bool "No clock selected (FTM counter disable)"
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config PWM_K64_FTM_0_CLOCK_SOURCE_SYSTEM
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bool "System clock"
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config PWM_K64_FTM_0_CLOCK_SOURCE_FIXED
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bool "Fixed Frequency Clock"
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config PWM_K64_FTM_0_CLOCK_SOURCE_EXTERNAL
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bool "External Clock"
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config PWM_K64_FTM_0_CLOCK_SOURCE_QUAD
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bool "Quadrature Decoder"
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endchoice
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endmenu
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config PWM_K64_FTM_0_CLOCK_SOURCE
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int
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# Omit prompt to signify "hidden" option
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depends on PWM_K64_FTM_0
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default 0 if PWM_K64_FTM_0_CLOCK_SOURCE_NONE
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default 1 if PWM_K64_FTM_0_CLOCK_SOURCE_SYSTEM
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default 2 if PWM_K64_FTM_0_CLOCK_SOURCE_FIXED
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default 3 if PWM_K64_FTM_0_CLOCK_SOURCE_EXTERNAL
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default 4 if PWM_K64_FTM_0_CLOCK_SOURCE_QUAD
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help
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Specify K64 FTM0 clock source
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config PWM_K64_FTM_0_PHASE_ENABLE_0
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bool "FTM0 Enable Phase for channel 0"
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depends on PWM_K64_FTM_0
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default n
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help
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Allow a phase offset on FTM0 channel 0. This configures
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channels 0 and 1 to be in combine mode therefore
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channel 1 is not valid as an output signal.
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Note: phase is an unsupported feature.
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config PWM_K64_FTM_0_PHASE_ENABLE_2
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bool "FTM0 Enable Phase for channel 2"
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depends on PWM_K64_FTM_0
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default n
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help
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Allow a phase offset on FTM0 channel 2. This configures
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channels 2 and 3 to be in combine mode therefore
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channel 3 is not valid as an output signal.
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Note: phase is an unsupported feature.
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config PWM_K64_FTM_0_PHASE_ENABLE_4
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bool "FTM0 Enable Phase for channel 4"
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depends on PWM_K64_FTM_0
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default n
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help
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Allow a phase offset on FTM0 channel 4. This configures
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channels 4 and 5 to be in combine mode therefore
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channel 5 is not valid as an output signal.
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Note: phase is an unsupported feature.
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config PWM_K64_FTM_0_PHASE_ENABLE_6
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bool "FTM0 Enable Phase for channel 6"
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depends on PWM_K64_FTM_0
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default n
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help
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Allow a phase offset on FTM0 channel 6. This configures
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channels 6 and 7 to be in combine mode therefore
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channel 7 is not valid as an output signal.
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Note: phase is an unsupported feature.
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#### FTM1 #####
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config PWM_K64_FTM_1
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bool "K64 FTM PWM Module 1"
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depends on PWM_K64_FTM
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default n
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help
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Enable config PWM options for FTM1 source module.
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config PWM_K64_FTM_1_DEV_NAME
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string "K64 FTM PWM Module 1 Device Name"
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depends on PWM_K64_FTM_1
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default "PWM_1"
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help
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Specify the device name for the FTM1 source module.
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config PWM_K64_FTM_1_PRESCALE
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int "FTM1 prescale value"
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default 1
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depends on PWM_K64_FTM_1
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help
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Specify the FTM1 timer prescale value. The valid values are
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1, 2, 4, 8, 16, 32, 64, or 128
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config PWM_K64_FTM_1_PERIOD
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int "FTM1 period value"
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default 65535
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depends on PWM_K64_FTM_1
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help
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Specify the FTM1 PWM period in ticks
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menu "K64 FTM1 Clock Source"
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depends on PWM_K64_FTM_1
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choice PWM_K64_FTM_1_CLOCK_SOURCE_CHOICE
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prompt "Choose the FTM1 clock source"
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default PWM_K64_FTM_1_CLOCK_SOURCE_SYSTEM
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config PWM_K64_FTM_1_CLOCK_SOURCE_NONE
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bool "No clock selected (FTM counter disable)"
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config PWM_K64_FTM_1_CLOCK_SOURCE_SYSTEM
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bool "System clock"
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config PWM_K64_FTM_1_CLOCK_SOURCE_FIXED
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bool "Fixed Frequency Clock"
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config PWM_K64_FTM_1_CLOCK_SOURCE_EXTERNAL
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bool "External Clock"
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config PWM_K64_FTM_1_CLOCK_SOURCE_QUAD
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bool "Quadrature Decoder"
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endchoice
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endmenu
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config PWM_K64_FTM_1_CLOCK_SOURCE
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int
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# Omit prompt to signify "hidden" option
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depends on PWM_K64_FTM_1
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default 0 if PWM_K64_FTM_1_CLOCK_SOURCE_NONE
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default 1 if PWM_K64_FTM_1_CLOCK_SOURCE_SYSTEM
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default 2 if PWM_K64_FTM_1_CLOCK_SOURCE_FIXED
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default 3 if PWM_K64_FTM_1_CLOCK_SOURCE_EXTERNAL
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default 4 if PWM_K64_FTM_1_CLOCK_SOURCE_QUAD
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help
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Specify K64 FTM1 clock source
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config PWM_K64_FTM_1_PHASE_ENABLE_0
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bool "FTM1 Enable Phase for channel 0"
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depends on PWM_K64_FTM_1
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default n
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help
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Allow a phase offset on FTM1 channel 0. This configures
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channels 0 and 1 to be in combine mode therefore
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channel 1 is not valid as an output signal.
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Note: phase is an unsupported feature.
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config PWM_FTM_1_PHASE_ENABLE_2
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bool "FTM1 Enable Phase for channel 2"
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depends on PWM_K64_FTM_1
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default n
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help
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Allow a phase offset on FTM1 channel 2. This configures
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channels 2 and 3 to be in combine mode therefore
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channel 3 is not valid as an output signal.
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Note: phase is an unsupported feature.
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config PWM_FTM_1_PHASE_ENABLE_4
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bool "FTM1 Enable Phase for channel 4"
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depends on PWM_K64_FTM_1
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default n
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help
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Allow a phase offset on FTM1 channel 4. This configures
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channels 4 and 5 to be in combine mode therefore
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channel 5 is not valid as an output signal.
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Note: phase is an unsupported feature.
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config PWM_FTM_1_PHASE_ENABLE_6
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bool "FTM1 Enable Phase for channel 6"
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depends on PWM_K64_FTM_1
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default n
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help
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Allow a phase offset on FTM1 channel 6. This configures
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channels 6 and 7 to be in combine mode therefore
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channel 7 is not valid as an output signal.
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Note: phase is an unsupported feature.
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#### FTM2 #####
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config PWM_K64_FTM_2
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bool "K64 FTM PWM Module 2"
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depends on PWM_K64_FTM
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default n
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help
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Enable config PWM options for FTM2 source module.
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config PWM_K64_FTM_2_DEV_NAME
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string "K64 FTM PWM Module 2 Device Name"
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depends on PWM_K64_FTM_2
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default "PWM_2"
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help
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Specify the device name for the FTM2 source module.
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config PWM_K64_FTM_2_PRESCALE
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int "FTM2 prescale value"
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default 1
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depends on PWM_K64_FTM_2
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help
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Specify the FTM2 timer prescale value. The valid values are
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1, 2, 4, 8, 16, 32, 64, or 128
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config PWM_K64_FTM_2_PERIOD
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int "FTM2 period value"
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default 65535
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depends on PWM_K64_FTM_2
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help
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Specify the FTM2 PWM period in ticks
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menu "K64 FTM2 Clock Source"
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depends on PWM_K64_FTM_2
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choice PWM_K64_FTM_2_CLOCK_SOURCE_CHOICE
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prompt "Choose the FTM2 clock source"
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default PWM_K64_FTM_2_CLOCK_SOURCE_SYSTEM
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config PWM_K64_FTM_2_CLOCK_SOURCE_NONE
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bool "No clock selected (FTM counter disable)"
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config PWM_K64_FTM_2_CLOCK_SOURCE_SYSTEM
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bool "System clock"
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config PWM_K64_FTM_2_CLOCK_SOURCE_FIXED
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bool "Fixed Frequency Clock"
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config PWM_K64_FTM_2_CLOCK_SOURCE_EXTERNAL
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bool "External Clock"
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config PWM_K64_FTM_2_CLOCK_SOURCE_QUAD
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bool "Quadrature Decoder"
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endchoice
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endmenu
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config PWM_K64_FTM_2_CLOCK_SOURCE
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int
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# Omit prompt to signify "hidden" option
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depends on PWM_K64_FTM_2
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default 0 if PWM_K64_FTM_2_CLOCK_SOURCE_NONE
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default 1 if PWM_K64_FTM_2_CLOCK_SOURCE_SYSTEM
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default 2 if PWM_K64_FTM_2_CLOCK_SOURCE_FIXED
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|
||||||
default 3 if PWM_K64_FTM_2_CLOCK_SOURCE_EXTERNAL
|
|
||||||
default 4 if PWM_K64_FTM_2_CLOCK_SOURCE_QUAD
|
|
||||||
help
|
|
||||||
Specify K64 FTM2 clock source
|
|
||||||
|
|
||||||
config PWM_K64_FTM_2_PHASE_ENABLE_0
|
|
||||||
bool "FTM2 Enable Phase for channel 0"
|
|
||||||
depends on PWM_K64_FTM_2
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM2 channel 0. This configures
|
|
||||||
channels 0 and 1 to be in combine mode therefore
|
|
||||||
channel 1 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_2_PHASE_ENABLE_2
|
|
||||||
bool "FTM2 Enable Phase for channel 2"
|
|
||||||
depends on PWM_K64_FTM_2
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM2 channel 2. This configures
|
|
||||||
channels 2 and 3 to be in combine mode therefore
|
|
||||||
channel 3 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_2_PHASE_ENABLE_4
|
|
||||||
bool "FTM2 Enable Phase for channel 4"
|
|
||||||
depends on PWM_K64_FTM_2
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM2 channel 4. This configures
|
|
||||||
channels 4 and 5 to be in combine mode therefore
|
|
||||||
channel 5 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_2_PHASE_ENABLE_6
|
|
||||||
bool "FTM2 Enable Phase for channel 6"
|
|
||||||
depends on PWM_K64_FTM_2
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM2 channel 6. This configures
|
|
||||||
channels 6 and 7 to be in combine mode therefore
|
|
||||||
channel 7 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
#### FTM3 #####
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3
|
|
||||||
bool "K64 FTM PWM Module 3"
|
|
||||||
depends on PWM_K64_FTM
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Enable config PWM options for K64 FTM3 source module.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_DEV_NAME
|
|
||||||
string "K64 FTM PWM Module 3 Device Name"
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
default "PWM_3"
|
|
||||||
help
|
|
||||||
Specify the device name for the FTM3 source module.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_PRESCALE
|
|
||||||
int "FTM3 prescale value"
|
|
||||||
default 3
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
help
|
|
||||||
Specify the FTM timer prescale value. The valid values are
|
|
||||||
1, 2, 4, 8, 16, 32, 64, or 128
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_PERIOD
|
|
||||||
int "FTM3 period value"
|
|
||||||
default 65535
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
help
|
|
||||||
Specify the FTM3 PWM period in ticks
|
|
||||||
|
|
||||||
menu "K64 FTM3 Clock Source"
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
|
|
||||||
choice PWM_K64_FTM_3_CLOCK_SOURCE_CHOICE
|
|
||||||
prompt "Choose the FTM3 clock source"
|
|
||||||
default PWM_K64_FTM_3_CLOCK_SOURCE_SYSTEM
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_CLOCK_SOURCE_NONE
|
|
||||||
bool "No clock selected (FTM counter disable)"
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_CLOCK_SOURCE_SYSTEM
|
|
||||||
bool "System clock"
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_CLOCK_SOURCE_FIXED
|
|
||||||
bool "Fixed Frequency Clock"
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_CLOCK_SOURCE_EXTERNAL
|
|
||||||
bool "External Clock"
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_CLOCK_SOURCE_QUAD
|
|
||||||
bool "Quadrature Decoder"
|
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
endmenu
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_CLOCK_SOURCE
|
|
||||||
int
|
|
||||||
# Omit prompt to signify "hidden" option
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
default 0 if PWM_K64_FTM_3_CLOCK_SOURCE_NONE
|
|
||||||
default 1 if PWM_K64_FTM_3_CLOCK_SOURCE_SYSTEM
|
|
||||||
default 2 if PWM_K64_FTM_3_CLOCK_SOURCE_FIXED
|
|
||||||
default 3 if PWM_K64_FTM_3_CLOCK_SOURCE_EXTERNAL
|
|
||||||
default 4 if PWM_K64_FTM_3_CLOCK_SOURCE_QUAD
|
|
||||||
help
|
|
||||||
Specify K64 FTM3 clock source
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_PHASE_ENABLE_0
|
|
||||||
bool "FTM3 Enable Phase for channel 0"
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM3 channel 0. This configures
|
|
||||||
channels 0 and 1 to be in combine mode therefore
|
|
||||||
channel 1 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_PHASE_ENABLE_2
|
|
||||||
bool "FTM3 Enable Phase for channel 2"
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM3 channel 2. This configures
|
|
||||||
channels 2 and 3 to be in combine mode therefore
|
|
||||||
channel 3 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_PHASE_ENABLE_4
|
|
||||||
bool "FTM3 Enable Phase for channel 4"
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM3 channel 4. This configures
|
|
||||||
channels 4 and 5 to be in combine mode therefore
|
|
||||||
channel 5 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
config PWM_K64_FTM_3_PHASE_ENABLE_6
|
|
||||||
bool "FTM3 Enable Phase for channel 6"
|
|
||||||
depends on PWM_K64_FTM_3
|
|
||||||
default n
|
|
||||||
help
|
|
||||||
Allow a phase offset on FTM3 channel 6. This configures
|
|
||||||
channels 6 and 7 to be in combine mode therefore
|
|
||||||
channel 7 is not valid as an output signal.
|
|
||||||
Note: phase is an unsupported feature.
|
|
||||||
|
|
||||||
endif # PWM_K64_FTM
|
|
||||||
|
|
@ -5,7 +5,6 @@ ccflags-$(CONFIG_PWM_QMSI) += -I$(CONFIG_QMSI_INSTALL_PATH)/include
|
||||||
obj-$(CONFIG_PWM_PCA9685) += pwm_pca9685.o
|
obj-$(CONFIG_PWM_PCA9685) += pwm_pca9685.o
|
||||||
obj-$(CONFIG_PWM_DW) += pwm_dw.o
|
obj-$(CONFIG_PWM_DW) += pwm_dw.o
|
||||||
obj-$(CONFIG_PWM_QMSI) += pwm_qmsi.o
|
obj-$(CONFIG_PWM_QMSI) += pwm_qmsi.o
|
||||||
obj-$(CONFIG_PWM_K64_FTM) += pwm_k64_ftm.o
|
|
||||||
obj-$(CONFIG_PWM_STM32) += pwm_stm32.o
|
obj-$(CONFIG_PWM_STM32) += pwm_stm32.o
|
||||||
obj-$(CONFIG_PWM_NRF5_SW) += pwm_nrf5_sw.o
|
obj-$(CONFIG_PWM_NRF5_SW) += pwm_nrf5_sw.o
|
||||||
obj-$(CONFIG_PWM_MCUX_FTM) += pwm_mcux_ftm.o
|
obj-$(CONFIG_PWM_MCUX_FTM) += pwm_mcux_ftm.o
|
||||||
|
|
|
||||||
|
|
@ -1,951 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Wind River Systems, Inc.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @file PWM driver for Freescale K64 FlexTimer Module (FTM)
|
|
||||||
*
|
|
||||||
* This file implements Pulse Width Modulation using the Freescale FlexTimer
|
|
||||||
* Module (FTM). Basic functionality is implemented using edge-aligned PWM
|
|
||||||
* mode. More complex functionality such as non-zero phase is not supported
|
|
||||||
* since combined mode operation is not implemented.
|
|
||||||
*
|
|
||||||
* The following configuration options are supported. ("x" can be one of the
|
|
||||||
* following values: 0, 1, 2, or 3 representing one of the four FMT modules
|
|
||||||
* FTM0, FTM1, FTM2, or FTM3.)
|
|
||||||
*
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_DEV_NAME: string representing the device name
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_PRESCALE: the clock prescaler value
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_CLOCK_SOURCE: the clock source
|
|
||||||
* - CONFIG_SYS_LOG_PWM_K64_FTM_LEVEL: sets log output level for the driver
|
|
||||||
* - CONFIG_STDOUT_CONSOLE: choose debug logs using printf of printk
|
|
||||||
*
|
|
||||||
* The following configuration options need to be defined in
|
|
||||||
* soc.h or board.h ("x" can be 0, 1, 2 or 3).
|
|
||||||
* - PWM_K64_FTM_x_REG_BASE: the base address of FTM (FTMx_SC)
|
|
||||||
*
|
|
||||||
* The following configuration options are not supported. These are place
|
|
||||||
* holders for future functionality
|
|
||||||
*
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_PHASE_ENABLE_0 support non-zero phase on channel 0
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_PHASE_ENABLE_1 support non-zero phase on channel 1
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_PHASE_ENABLE_2 support non-zero phase on channel 2
|
|
||||||
* - CONFIG_PWM_K64_FTM_x_PHASE_ENABLE_3 support non-zero phase on channel 3
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#include <kernel.h>
|
|
||||||
|
|
||||||
#include <board.h>
|
|
||||||
#include <k20_sim.h>
|
|
||||||
#include <power.h>
|
|
||||||
#include <pwm.h>
|
|
||||||
|
|
||||||
#include "pwm_k64_ftm.h"
|
|
||||||
#include <stdio.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Non-zero phase is not supported because combine mode is not yet
|
|
||||||
* implemented.
|
|
||||||
*/
|
|
||||||
#undef COMBINE_MODE_SUPPORT
|
|
||||||
|
|
||||||
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_PWM_K64_FTM_LEVEL
|
|
||||||
#include <logging/sys_log.h>
|
|
||||||
|
|
||||||
/* Maximum PWM outputs */
|
|
||||||
#define MAX_PWM_OUT 8
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the clock for the FTM subsystem
|
|
||||||
*
|
|
||||||
* This function must be called before writing to FTM registers. Failure to
|
|
||||||
* do so may result in bus fault.
|
|
||||||
*
|
|
||||||
* @param ftm_num index indicating which FTM
|
|
||||||
*
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int pwm_ftm_clk_enable(u8_t ftm_num)
|
|
||||||
{
|
|
||||||
|
|
||||||
volatile struct K20_SIM *sim =
|
|
||||||
(volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM; /* sys integ. ctl */
|
|
||||||
|
|
||||||
if (ftm_num > 3) {
|
|
||||||
SYS_LOG_ERR("Illegal FTM number (%d).\n Cannot enable PWM "
|
|
||||||
"clock", ftm_num);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enabling the FTM by setting one of the bits SIM_SCGC6[26:24] */
|
|
||||||
|
|
||||||
sim->scgc6 |= 1 << (24 + ftm_num);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initial FTM configuration
|
|
||||||
*
|
|
||||||
* Initialize the FTM hardware based on configuration options.
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @param access_op Access operation (pin or port)
|
|
||||||
* @param channel The pwm channel number
|
|
||||||
* @param flags Device flags (unused)
|
|
||||||
*
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int pwm_ftm_configure(struct device *dev, int access_op,
|
|
||||||
u32_t channel, int flags)
|
|
||||||
{
|
|
||||||
int return_val = 0;
|
|
||||||
|
|
||||||
u32_t clock_source;
|
|
||||||
u32_t prescale;
|
|
||||||
u32_t polarity;
|
|
||||||
|
|
||||||
u32_t reg_val;
|
|
||||||
|
|
||||||
|
|
||||||
SYS_LOG_DBG("...");
|
|
||||||
|
|
||||||
const struct pwm_ftm_config * const config =
|
|
||||||
dev->config->config_info;
|
|
||||||
|
|
||||||
ARG_UNUSED(access_op);
|
|
||||||
ARG_UNUSED(flags);
|
|
||||||
|
|
||||||
/* enable the clock for the FTM subsystem */
|
|
||||||
pwm_ftm_clk_enable(config->ftm_num);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize:
|
|
||||||
* clock source = x (system, fixed, external) from config
|
|
||||||
* prescaler divide-by x=(1,2,4,8,16,32,64,128) from config
|
|
||||||
* free-running count-up
|
|
||||||
* edge-aligned PWM mode
|
|
||||||
* pair: independent outputs
|
|
||||||
* polarity +
|
|
||||||
* no interrupt
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PS[2:0] = prescale
|
|
||||||
* MOD = pulse width
|
|
||||||
*/
|
|
||||||
|
|
||||||
clock_source = (config->clock_source & 0x3) << PWM_K64_FTM_SC_CLKS_SHIFT;
|
|
||||||
|
|
||||||
if (clock_source == 0) {
|
|
||||||
SYS_LOG_DBG("Warning: no clock source. PWM is disabled");
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
switch (config->prescale) {
|
|
||||||
case PWM_K64_FTM_PRESCALE_1:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D1;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_2:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D2;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_4:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D4;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_8:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D8;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_16:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D16;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_32:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D32;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_64:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D64;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case PWM_K64_FTM_PRESCALE_128:
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D128;
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
/* Illegal prescale value. Default to 1. */
|
|
||||||
prescale = PWM_K64_FTM_SC_PS_D1;
|
|
||||||
return_val = -ENOTSUP;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef COMBINE_MODE_SUPPORT
|
|
||||||
/* Enable FTMEN=1 and set outputs to initial value */
|
|
||||||
mode_reg_val = sys_read32(PWM_K64_FTM_MODE(config->reg_base));
|
|
||||||
mode_reg_val |= PWM_K64_FTM_MODE_FTMEN | PWM_K64_FTM_MODE_INIT;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
mode_reg_val, PWM_K64_FTM_MODE(config->reg_base));
|
|
||||||
|
|
||||||
sys_write32(mode_reg_val, PWM_K64_FTM_MODE(config->reg_base));
|
|
||||||
|
|
||||||
/* Enable enhanced synchronization */
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
PWM_K64_FTM_SYNCONF_SYNCMODE|PWM_K64_FTM_SYNCONF_CNTINC,
|
|
||||||
PWM_K64_FTM_SYNCONF(config->reg_base));
|
|
||||||
|
|
||||||
sys_write32(PWM_K64_FTM_SYNCONF_SYNCMODE|PWM_K64_FTM_SYNCONF_CNTINC,
|
|
||||||
PWM_K64_FTM_SYNCONF(config->reg_base));
|
|
||||||
|
|
||||||
#endif /*COMBINE_MODE_SUPPORT*/
|
|
||||||
|
|
||||||
/* Configure: PS | CLKS | up-counter | disable TOF intr */
|
|
||||||
reg_val = prescale | clock_source;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
reg_val, PWM_K64_FTM_SC(config->reg_base));
|
|
||||||
|
|
||||||
sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
config->period, PWM_K64_FTM_MOD(config->reg_base));
|
|
||||||
|
|
||||||
/* set MOD to max */
|
|
||||||
sys_write32(config->period, PWM_K64_FTM_MOD(config->reg_base));
|
|
||||||
|
|
||||||
/* set channel control to edge-aligned */
|
|
||||||
reg_val = PWM_K64_FTM_CNSC_MSB | PWM_K64_FTM_CNSC_ELSB;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
reg_val, PWM_K64_FTM_CNSC(config->reg_base, channel));
|
|
||||||
|
|
||||||
sys_write32(reg_val, PWM_K64_FTM_CNSC(config->reg_base, channel));
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_read32 4..");
|
|
||||||
|
|
||||||
/* set polarity high for this channel */
|
|
||||||
polarity = sys_read32(PWM_K64_FTM_POL(config->reg_base));
|
|
||||||
polarity &= ~(1<<channel);
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
polarity, PWM_K64_FTM_POL(config->reg_base));
|
|
||||||
|
|
||||||
sys_write32(polarity, PWM_K64_FTM_POL(config->reg_base));
|
|
||||||
|
|
||||||
return return_val;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief API call to set the on/off timer values
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @param access_op Access operation (pin or port)
|
|
||||||
* @param channel The pwm channel number
|
|
||||||
* @param on Timer count value for the start of the pulse on each cycle
|
|
||||||
* (must be 0)
|
|
||||||
* @param off Timer count value for the end of the pulse. After this, the
|
|
||||||
* signal will be off (low if positive polarity) for the rest of
|
|
||||||
* the cycle.
|
|
||||||
*
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int pwm_ftm_set_values(struct device *dev, int access_op,
|
|
||||||
u32_t channel, u32_t on, u32_t off)
|
|
||||||
{
|
|
||||||
const struct pwm_ftm_config * const config =
|
|
||||||
dev->config->config_info;
|
|
||||||
struct pwm_ftm_drv_data * const drv_data =
|
|
||||||
(struct pwm_ftm_drv_data * const)dev->driver_data;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("(on=%d, off=%d)", on, off);
|
|
||||||
|
|
||||||
u32_t pwm_pair;
|
|
||||||
u32_t combine;
|
|
||||||
|
|
||||||
switch (access_op) {
|
|
||||||
case PWM_ACCESS_BY_PIN:
|
|
||||||
break;
|
|
||||||
case PWM_ACCESS_ALL:
|
|
||||||
return -ENOTSUP;
|
|
||||||
default:
|
|
||||||
return -ENOTSUP;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* If either ON and/or OFF > max ticks, treat PWM as 100%.
|
|
||||||
* If OFF value == 0, treat it as 0%.
|
|
||||||
* Otherwise, populate registers accordingly.
|
|
||||||
*/
|
|
||||||
|
|
||||||
if ((on >= config->period) || (off >= config->period)) {
|
|
||||||
/* Fully on. Set to 100% */
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
config->period, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
/* CnV = pulse width */
|
|
||||||
sys_write32(config->period, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
} else if (off == 0) {
|
|
||||||
/* Fully off. Set to 0% */
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
0, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
/* CnV = 0 */
|
|
||||||
sys_write32(0, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
} else {
|
|
||||||
|
|
||||||
|
|
||||||
/* if on != 0 then set to combine mode and pwm must be even */
|
|
||||||
if (on != 0) {
|
|
||||||
|
|
||||||
#ifdef COMBINE_MODE_SUPPORT
|
|
||||||
/* TODO should verify that the other channel is not in
|
|
||||||
* use in non-combine mode
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* If phase != 0 enable combine mode */
|
|
||||||
if (channel % 2 != 0) {
|
|
||||||
SYS_LOG_DBG("If Phase is non-zero pwm must be "
|
|
||||||
"0, 2, 4, 6.");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
SYS_LOG_DBG("Note: Enabling phase on pwm%d therefore "
|
|
||||||
"pwm%d is not valid for output", channel,
|
|
||||||
channel+1);
|
|
||||||
|
|
||||||
pwm_pair = channel / 2;
|
|
||||||
|
|
||||||
/* verify that the pair is configured for non-zero phase */
|
|
||||||
switch (pwm_pair) {
|
|
||||||
case 0:
|
|
||||||
if (!config->phase_enable0) {
|
|
||||||
SYS_LOG_ERR("Phase capability must be "
|
|
||||||
"enabled on FTM0");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 1:
|
|
||||||
if (!config->phase_enable2) {
|
|
||||||
SYS_LOG_ERR("Phase capability must be "
|
|
||||||
"enabled on FTM2");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
drv_data->phase[1] = on;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 2:
|
|
||||||
if (!config->phase_enable4) {
|
|
||||||
SYS_LOG_ERR("Phase capability must be "
|
|
||||||
"enabled on FTM4");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 3:
|
|
||||||
if (!config->phase_enable6) {
|
|
||||||
SYS_LOG_ERR("Phase capability must be "
|
|
||||||
"enabled on FTM0");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
drv_data->phase[pwm_pair] = on;
|
|
||||||
|
|
||||||
combine =
|
|
||||||
sys_read32(PWM_K64_FTM_COMBINE(config->reg_base));
|
|
||||||
combine |= 1 << (pwm_pair * 8);
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
combine, PWM_K64_FTM_COMBINE(config->reg_base));
|
|
||||||
|
|
||||||
sys_write32(combine, PWM_K64_FTM_COMBINE(config->reg_base));
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
on, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
/* set the on value */
|
|
||||||
sys_write32(on, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
off, PWM_K64_FTM_CNV(config->reg_base, channel+1));
|
|
||||||
|
|
||||||
/* set the off value */
|
|
||||||
sys_write32(off, PWM_K64_FTM_CNV(config->reg_base, channel+1));
|
|
||||||
#else /*COMBINE_MODE_SUPPORT*/
|
|
||||||
SYS_LOG_ERR("\"on\" value must be zero. Phase "
|
|
||||||
"is not supported");
|
|
||||||
return -EINVAL;
|
|
||||||
#endif /*COMBINE_MODE_SUPPORT*/
|
|
||||||
|
|
||||||
} else {
|
|
||||||
|
|
||||||
/* zero phase. No need to combine two channels. */
|
|
||||||
|
|
||||||
if (channel % 2 != 0) {
|
|
||||||
pwm_pair = (channel - 1) / 2;
|
|
||||||
} else {
|
|
||||||
pwm_pair = channel / 2;
|
|
||||||
}
|
|
||||||
|
|
||||||
drv_data->phase[pwm_pair] = 0;
|
|
||||||
|
|
||||||
combine =
|
|
||||||
sys_read32(PWM_K64_FTM_COMBINE(config->reg_base));
|
|
||||||
combine &= ~(1 << (pwm_pair * 8));
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
combine, PWM_K64_FTM_COMBINE(config->reg_base));
|
|
||||||
|
|
||||||
sys_write32(combine, PWM_K64_FTM_COMBINE(config->reg_base));
|
|
||||||
|
|
||||||
/* set the off value */
|
|
||||||
|
|
||||||
SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
|
|
||||||
off, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
|
|
||||||
sys_write32(off, PWM_K64_FTM_CNV(config->reg_base, channel));
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
SYS_LOG_DBG("done.");
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief API call to set the duty cycle
|
|
||||||
*
|
|
||||||
* Duty cycle describes the percentage of time a signal is in the ON state.
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @param access_op Access operation (pin or port)
|
|
||||||
* @param channel The pwm channel number
|
|
||||||
* @param duty Percentage of time signal is on (value between 0 and 100)
|
|
||||||
*
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int pwm_ftm_set_duty_cycle(struct device *dev, int access_op,
|
|
||||||
u32_t channel, u8_t duty)
|
|
||||||
{
|
|
||||||
u32_t on, off;
|
|
||||||
|
|
||||||
const struct pwm_ftm_config * const config =
|
|
||||||
dev->config->config_info;
|
|
||||||
struct pwm_ftm_drv_data * const drv_data =
|
|
||||||
(struct pwm_ftm_drv_data * const)dev->driver_data;
|
|
||||||
|
|
||||||
ARG_UNUSED(access_op);
|
|
||||||
|
|
||||||
SYS_LOG_DBG("...");
|
|
||||||
|
|
||||||
if (duty == 0) {
|
|
||||||
/* Turn off PWM */
|
|
||||||
on = 0;
|
|
||||||
off = 0;
|
|
||||||
} else if (duty >= 100) {
|
|
||||||
/* Force PWM to be 100% */
|
|
||||||
on = 0;
|
|
||||||
off = config->period + 1;
|
|
||||||
} else {
|
|
||||||
|
|
||||||
on = 0;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set the "on" value to the phase offset if it was set by
|
|
||||||
* pwm_ftm_set_phase()
|
|
||||||
*/
|
|
||||||
|
|
||||||
switch (channel) {
|
|
||||||
case 0:
|
|
||||||
if (config->phase_enable0)
|
|
||||||
on = drv_data->phase[0];
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 2:
|
|
||||||
if (config->phase_enable2)
|
|
||||||
on = drv_data->phase[1];
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 4:
|
|
||||||
if (config->phase_enable4)
|
|
||||||
on = drv_data->phase[2];
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 6:
|
|
||||||
if (config->phase_enable6)
|
|
||||||
on = drv_data->phase[3];
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* Calculate the timer value for when to stop the pulse */
|
|
||||||
|
|
||||||
off = on + config->period * duty / 100;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("on=%d, off=%d, period=%d, duty=%d.",
|
|
||||||
on, off, config->period, duty);
|
|
||||||
|
|
||||||
/* check for valid off value */
|
|
||||||
if (off > config->period)
|
|
||||||
return -ENOTSUP;
|
|
||||||
}
|
|
||||||
|
|
||||||
return pwm_ftm_set_values(dev, access_op, channel, on, off);
|
|
||||||
|
|
||||||
SYS_LOG_DBG("done.");
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief API call to set the phase
|
|
||||||
*
|
|
||||||
* Phase describes number of clock ticks of delay before the start of the
|
|
||||||
* pulse. The maximum count of the FTM timer is 65536 so the phase value is
|
|
||||||
* an integer from 0 to 65536.
|
|
||||||
*
|
|
||||||
* A non-zero phase value requires the timer pair to be set to combined mode
|
|
||||||
* so the odd-numbered (n+1) channel is not available for output
|
|
||||||
*
|
|
||||||
* Note: non-zero phase is not supported in this implementation
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @param access_op Access operation (pin or port)
|
|
||||||
* @param channel The pwm channel number
|
|
||||||
* @param phase Clock ticks of delay before start of the pulse (must be 0)
|
|
||||||
*
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int pwm_ftm_set_phase(struct device *dev, int access_op,
|
|
||||||
u32_t channel, u8_t phase)
|
|
||||||
{
|
|
||||||
|
|
||||||
#ifdef COMBINE_MODE_SUPPORT
|
|
||||||
const struct pwm_ftm_config * const config =
|
|
||||||
dev->config->config_info;
|
|
||||||
struct pwm_ftm_drv_data * const drv_data =
|
|
||||||
(struct pwm_ftm_drv_data * const)dev->driver_data;
|
|
||||||
|
|
||||||
ARG_UNUSED(access_op);
|
|
||||||
|
|
||||||
SYS_LOG_DBG("...");
|
|
||||||
|
|
||||||
if ((phase < 0) || (phase > config->period))
|
|
||||||
return -ENOTSUP;
|
|
||||||
|
|
||||||
switch (channel) {
|
|
||||||
case 0:
|
|
||||||
if (!config->phase_enable0)
|
|
||||||
return -ENOTSUP;
|
|
||||||
drv_data->phase[0] = phase;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 2:
|
|
||||||
if (!config->phase_enable2)
|
|
||||||
return -ENOTSUP;
|
|
||||||
drv_data->phase[1] = phase;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 4:
|
|
||||||
if (!config->phase_enable4)
|
|
||||||
return -ENOTSUP;
|
|
||||||
drv_data->phase[2] = phase;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 6:
|
|
||||||
if (!config->phase_enable6)
|
|
||||||
return -ENOTSUP;
|
|
||||||
drv_data->phase[3] = phase;
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
/* channel must be 0, 2, 4, or 6 */
|
|
||||||
return -ENOTSUP;
|
|
||||||
}
|
|
||||||
|
|
||||||
SYS_LOG_DBG("done.");
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
#else /*COMBINE_MODE_SUPPORT*/
|
|
||||||
|
|
||||||
ARG_UNUSED(dev);
|
|
||||||
ARG_UNUSED(access_op);
|
|
||||||
ARG_UNUSED(channel);
|
|
||||||
ARG_UNUSED(phase);
|
|
||||||
|
|
||||||
SYS_LOG_ERR("non-zero phase is not supported.");
|
|
||||||
|
|
||||||
return -ENOTSUP;
|
|
||||||
#endif /*COMBINE_MODE_SUPPORT*/
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
||||||
/**
|
|
||||||
* @brief API to set device power state
|
|
||||||
*
|
|
||||||
* This function simply sets the device power state in driver_data
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @param power_state device power state to be saved
|
|
||||||
* @return N/A
|
|
||||||
*/
|
|
||||||
static void pwm_ftm_set_power_state(struct device *dev, u32_t power_state)
|
|
||||||
{
|
|
||||||
struct pwm_ftm_drv_data *context = dev->driver_data;
|
|
||||||
|
|
||||||
context->device_power_state = power_state;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief API to get device power state
|
|
||||||
*
|
|
||||||
* This function simply returns the device power state
|
|
||||||
* from driver_data
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @return device power state
|
|
||||||
*/
|
|
||||||
static u32_t pwm_ftm_get_power_state(struct device *dev)
|
|
||||||
{
|
|
||||||
struct pwm_ftm_drv_data *context = dev->driver_data;
|
|
||||||
|
|
||||||
return context->device_power_state;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief API call to disable FTM
|
|
||||||
*
|
|
||||||
* This function simply sets the clock source to "no clock selected" thus
|
|
||||||
* disabling the FTM
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int pwm_ftm_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
u32_t reg_val;
|
|
||||||
|
|
||||||
const struct pwm_ftm_config * const config =
|
|
||||||
dev->config->config_info;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("...");
|
|
||||||
|
|
||||||
/* set clock source to "no clock selected" */
|
|
||||||
|
|
||||||
reg_val = sys_read32(PWM_K64_FTM_SC(config->reg_base));
|
|
||||||
|
|
||||||
reg_val &= ~PWM_K64_FTM_SC_CLKS_MASK;
|
|
||||||
|
|
||||||
reg_val |= PWM_K64_FTM_SC_CLKS_DISABLE;
|
|
||||||
|
|
||||||
sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
|
|
||||||
|
|
||||||
pwm_ftm_set_power_state(DEVICE_PM_SUSPEND_STATE);
|
|
||||||
SYS_LOG_DBG("done.");
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief API call to reenable FTM
|
|
||||||
*
|
|
||||||
* This function simply sets the clock source to the configuration value with
|
|
||||||
* the assumption that FTM was previously disabled by setting the clock source
|
|
||||||
* to "no clock selected" due to a call to pwm_ftm_suspend.
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
static int pwm_ftm_resume_from_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
u32_t clock_source;
|
|
||||||
u32_t reg_val;
|
|
||||||
|
|
||||||
/* set clock source to config value */
|
|
||||||
|
|
||||||
const struct pwm_ftm_config * const config =
|
|
||||||
dev->config->config_info;
|
|
||||||
|
|
||||||
SYS_LOG_DBG("...");
|
|
||||||
|
|
||||||
clock_source = (config->clock_source << PWM_K64_FTM_SC_CLKS_SHIFT) &&
|
|
||||||
PWM_K64_FTM_SC_CLKS_MASK;
|
|
||||||
|
|
||||||
reg_val = sys_read32(PWM_K64_FTM_SC(config->reg_base));
|
|
||||||
|
|
||||||
reg_val &= ~PWM_K64_FTM_SC_CLKS_MASK;
|
|
||||||
|
|
||||||
reg_val |= clock_source;
|
|
||||||
|
|
||||||
sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
|
|
||||||
|
|
||||||
pwm_ftm_set_power_state(DEVICE_PM_ACTIVE_STATE);
|
|
||||||
|
|
||||||
SYS_LOG_DBG("done.");
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Implements the driver control management functionality
|
|
||||||
* the *context may include IN data or/and OUT data
|
|
||||||
*/
|
|
||||||
static int pwm_ftm_device_ctrl(struct device *dev, u32_t ctrl_command,
|
|
||||||
void *context)
|
|
||||||
{
|
|
||||||
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
|
|
||||||
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
|
|
||||||
return pwm_ftm_suspend(dev);
|
|
||||||
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
|
|
||||||
return pwm_ftm_resume_from_suspend(dev);
|
|
||||||
}
|
|
||||||
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
|
|
||||||
*((u32_t *)context) = pwm_ftm_get_power_state(dev);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define pwm_ftm_set_power_state(...)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
static const struct pwm_driver_api pwm_ftm_drv_api_funcs = {
|
|
||||||
.config = pwm_ftm_configure,
|
|
||||||
.set_values = pwm_ftm_set_values,
|
|
||||||
.set_duty_cycle = pwm_ftm_set_duty_cycle,
|
|
||||||
.set_phase = pwm_ftm_set_phase,
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initialization function of FTM
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @return 0 if successful, failed otherwise.
|
|
||||||
*/
|
|
||||||
int pwm_ftm_init(struct device *dev)
|
|
||||||
{
|
|
||||||
|
|
||||||
SYS_LOG_DBG("...");
|
|
||||||
pwm_ftm_set_power_state(DEVICE_PM_ACTIVE_STATE);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialization for PWM_K64_FTM_0 */
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_0
|
|
||||||
#include <device.h>
|
|
||||||
#include <init.h>
|
|
||||||
|
|
||||||
static const struct pwm_ftm_config pwm_ftm_0_cfg = {
|
|
||||||
.ftm_num = 0,
|
|
||||||
.reg_base = PWM_K64_FTM_0_REG_BASE,
|
|
||||||
.prescale = CONFIG_PWM_K64_FTM_0_PRESCALE,
|
|
||||||
.clock_source = CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE,
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_0
|
|
||||||
.phase_enable0 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable0 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_2
|
|
||||||
.phase_enable2 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable2 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_4
|
|
||||||
.phase_enable4 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable4 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_6
|
|
||||||
.phase_enable6 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable6 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.period = CONFIG_PWM_K64_FTM_0_PERIOD,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct pwm_ftm_drv_data pwm_ftm_0_drvdata;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(pwm_ftm_0, CONFIG_PWM_K64_FTM_0_DEV_NAME, pwm_ftm_init,
|
|
||||||
pwm_ftm_device_ctrl, &pwm_ftm_0_drvdata, &pwm_ftm_0_cfg,
|
|
||||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
||||||
&pwm_ftm_drv_api_funcs);
|
|
||||||
|
|
||||||
#endif /* CONFIG_PWM_K64_FTM_0 */
|
|
||||||
|
|
||||||
/* Initialization for PWM_K64_FTM_1 */
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_1
|
|
||||||
#include <device.h>
|
|
||||||
#include <init.h>
|
|
||||||
|
|
||||||
static const struct pwm_ftm_config pwm_ftm_1_cfg = {
|
|
||||||
.ftm_num = 1,
|
|
||||||
.reg_base = PWM_K64_FTM_1_REG_BASE,
|
|
||||||
.prescale = CONFIG_PWM_K64_FTM_1_PRESCALE,
|
|
||||||
.clock_source = CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE,
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_1_PHASE_ENABLE_0
|
|
||||||
.phase_enable0 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable0 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_1_PHASE_ENABLE_2
|
|
||||||
.phase_enable2 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable2 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_1_PHASE_ENABLE_4
|
|
||||||
.phase_enable4 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable4 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_1_PHASE_ENABLE_6
|
|
||||||
.phase_enable6 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable6 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct pwm_ftm_drv_data pwm_ftm_1_drvdata;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(pwm_ftm_1, CONFIG_PWM_K64_FTM_1_DEV_NAME, pwm_ftm_init,
|
|
||||||
pwm_ftm_device_ctrl, &pwm_ftm_1_drvdata, &pwm_ftm_1_cfg,
|
|
||||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
||||||
&pwm_ftm_drv_api_funcs);
|
|
||||||
|
|
||||||
#endif /* CONFIG_PWM_K64_FTM_1 */
|
|
||||||
|
|
||||||
|
|
||||||
/* Initialization for PWM_K64_FTM_2 */
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_2
|
|
||||||
#include <device.h>
|
|
||||||
#include <init.h>
|
|
||||||
|
|
||||||
static const struct pwm_ftm_config pwm_ftm_2_cfg = {
|
|
||||||
.ftm_num = 2,
|
|
||||||
.reg_base = PWM_K64_FTM_2_REG_BASE,
|
|
||||||
.prescale = CONFIG_PWM_K64_FTM_2_PRESCALE,
|
|
||||||
.clock_source = CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE,
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_0
|
|
||||||
.phase_enable0 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable0 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_2
|
|
||||||
.phase_enable2 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable2 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_4
|
|
||||||
.phase_enable4 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable4 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_6
|
|
||||||
.phase_enable6 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable6 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct pwm_ftm_drv_data pwm_ftm_2_drvdata;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(pwm_ftm_2, CONFIG_PWM_K64_FTM_2_DEV_NAME, pwm_ftm_init,
|
|
||||||
pwm_ftm_device_ctrl, &pwm_ftm_2_drvdata, &pwm_ftm_2_cfg,
|
|
||||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
||||||
&pwm_ftm_drv_api_funcs);
|
|
||||||
|
|
||||||
#endif /* CONFIG_PWM_K64_FTM_2 */
|
|
||||||
|
|
||||||
|
|
||||||
/* Initialization for PWM_K64_FTM_3 */
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_3
|
|
||||||
#include <device.h>
|
|
||||||
#include <init.h>
|
|
||||||
|
|
||||||
static const struct pwm_ftm_config pwm_ftm_3_cfg = {
|
|
||||||
.ftm_num = 3,
|
|
||||||
.reg_base = PWM_K64_FTM_3_REG_BASE,
|
|
||||||
.prescale = CONFIG_PWM_K64_FTM_3_PRESCALE,
|
|
||||||
.clock_source = CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE,
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_0
|
|
||||||
.phase_enable0 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable0 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_2
|
|
||||||
.phase_enable2 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable2 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_4
|
|
||||||
.phase_enable4 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable4 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_6
|
|
||||||
.phase_enable6 = 1,
|
|
||||||
#else
|
|
||||||
.phase_enable6 = 0,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct pwm_ftm_drv_data pwm_ftm_3_drvdata;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(pwm_ftm_3, CONFIG_PWM_K64_FTM_3_DEV_NAME, pwm_ftm_init,
|
|
||||||
pwm_ftm_device_ctrl, &pwm_ftm_3_drvdata, &pwm_ftm_3_cfg,
|
|
||||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
||||||
&pwm_ftm_drv_api_funcs);
|
|
||||||
|
|
||||||
#endif /* CONFIG_PWM_K64_FTM_3 */
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Wind River Systems, Inc.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @file Header file for the PWM driver for Freescale K64 FlexTimer Module (FTM)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __PWM_K64_FTM_H__
|
|
||||||
#define __PWM_K64_FTM_H__
|
|
||||||
|
|
||||||
#include <stdbool.h>
|
|
||||||
|
|
||||||
/* Valid prescale values */
|
|
||||||
#define PWM_K64_FTM_PRESCALE_1 1
|
|
||||||
#define PWM_K64_FTM_PRESCALE_2 2
|
|
||||||
#define PWM_K64_FTM_PRESCALE_4 4
|
|
||||||
#define PWM_K64_FTM_PRESCALE_8 8
|
|
||||||
#define PWM_K64_FTM_PRESCALE_16 16
|
|
||||||
#define PWM_K64_FTM_PRESCALE_32 32
|
|
||||||
#define PWM_K64_FTM_PRESCALE_64 64
|
|
||||||
#define PWM_K64_FTM_PRESCALE_128 128
|
|
||||||
|
|
||||||
/* flags are not used. This value can be passed into pwm_pin_configure */
|
|
||||||
#define PWM_K64_FTM_FLAG_NONE 0
|
|
||||||
|
|
||||||
|
|
||||||
/* FTM register bit definitions */
|
|
||||||
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_SC(base) ((base)+0x00) /* Status And Control */
|
|
||||||
#define PWM_K64_FTM_CNT(base) ((base)+0x04) /* Counter */
|
|
||||||
#define PWM_K64_FTM_MOD(base) ((base)+0x08) /* Modulo */
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_CNSC(base, ch) ((base)+0x0C+(ch)*8) /* Channel Status&Ctrl*/
|
|
||||||
#define PWM_K64_FTM_CNV(base, ch) ((base)+0x10+(ch)*8) /* Channel Value */
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_CNTIN(base) ((base)+0x4C) /* Counter Initial Value */
|
|
||||||
#define PWM_K64_FTM_STATUS(base) ((base)+0x50) /* Capture And Compare Status*/
|
|
||||||
#define PWM_K64_FTM_MODE(base) ((base)+0x54) /* Features Mode Selection */
|
|
||||||
#define PWM_K64_FTM_SYNC(base) ((base)+0x58) /* Synchronization */
|
|
||||||
#define PWM_K64_FTM_OUTINIT(base) ((base)+0x5C) /* Initial Channels Output */
|
|
||||||
#define PWM_K64_FTM_OUTMASK(base) ((base)+0x60) /* Output Mask */
|
|
||||||
#define PWM_K64_FTM_COMBINE(base) ((base)+0x64) /* Function For Linked Chans */
|
|
||||||
#define PWM_K64_FTM_DEADTIME(base) ((base)+0x68) /* Deadtime Insertion Ctrl */
|
|
||||||
#define PWM_K64_FTM_EXTTRIG(base) ((base)+0x6C) /* FTM External Trigger */
|
|
||||||
#define PWM_K64_FTM_POL(base) ((base)+0x70) /* Channels Polarity */
|
|
||||||
#define PWM_K64_FTM_FMS(base) ((base)+0x74) /* Fault Mode Status */
|
|
||||||
#define PWM_K64_FTM_FILTER(base) ((base)+0x78) /* Input Capture Filter Ctrl */
|
|
||||||
#define PWM_K64_FTM_FLTCTRL(base) ((base)+0x7C) /* Fault Control */
|
|
||||||
#define PWM_K64_FTM_QDCTRL(base) ((base)+0x80) /* Quadrature Decoder Ctrl */
|
|
||||||
#define PWM_K64_FTM_CONF(base) ((base)+0x84) /* Configuration */
|
|
||||||
#define PWM_K64_FTM_FLTPOL(base) ((base)+0x88) /* FTM Fault Input Polarity */
|
|
||||||
#define PWM_K64_FTM_SYNCONF(base) ((base)+0x8C) /* Synchronization Config */
|
|
||||||
#define PWM_K64_FTM_INVCTRL(base) ((base)+0x90) /* FTM Inverting Control */
|
|
||||||
#define PWM_K64_FTM_SWOCTRL(base) ((base)+0x94) /* FTM Software Output Ctrl */
|
|
||||||
#define PWM_K64_FTM_PWMLOAD(base) ((base)+0x98) /* FTM PWM Load */
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_SC Status And Control */
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_SC_CLKS_MASK 0x18
|
|
||||||
#define PWM_K64_FTM_SC_CLKS_SHIFT 3
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_SC_CLKS_DISABLE 0x0
|
|
||||||
#define PWM_K64_FTM_SC_CLKS_SYSTEM 0x1
|
|
||||||
#define PWM_K64_FTM_SC_CLKS_FIXED 0x2
|
|
||||||
#define PWM_K64_FTM_SC_CLKS_EXTERNAL 0x3
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_SC_PS_D1 (0x0<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D2 (0x1<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D4 (0x2<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D8 (0x3<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D16 (0x4<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D32 (0x5<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D64 (0x6<<0)
|
|
||||||
#define PWM_K64_FTM_SC_PS_D128 (0x7<<0)
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_SC_PS_MASK (0x7<<0)
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_CNSC (FTMx_CnSC) Channel-n Status And Control */
|
|
||||||
#define PWM_K64_FTM_CNSC_DMA (0x1<<0)
|
|
||||||
#define PWM_K64_FTM_CNSC_ELSA (0x1<<2)
|
|
||||||
#define PWM_K64_FTM_CNSC_ELSB (0x1<<3)
|
|
||||||
#define PWM_K64_FTM_CNSC_MSA (0x1<<4)
|
|
||||||
#define PWM_K64_FTM_CNSC_MSB (0x1<<5)
|
|
||||||
#define PWM_K64_FTM_CNSC_CHIE (0x1<<6)
|
|
||||||
#define PWM_K64_FTM_CNSC_CHF (0x1<<7)
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_MODE Features Mode Selection */
|
|
||||||
#define PWM_K64_FTM_MODE_FTMEN (0x1<<0)
|
|
||||||
#define PWM_K64_FTM_MODE_INIT (0x1<<1)
|
|
||||||
#define PWM_K64_FTM_MODE_WPDIS (0x1<<2)
|
|
||||||
#define PWM_K64_FTM_MODE_PWMSYNC (0x1<<3)
|
|
||||||
#define PWM_K64_FTM_MODE_CAPTEST (0x1<<4)
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_MODE_FAULTM_DISABLE (0x0<<5)
|
|
||||||
#define PWM_K64_FTM_MODE_FAULTM_EVEN (0x1<<5)
|
|
||||||
#define PWM_K64_FTM_MODE_FAULTM_MANUAL (0x2<<5)
|
|
||||||
#define PWM_K64_FTM_MODE_FAULTM_AUTO (0x3<<5)
|
|
||||||
#define PWM_K64_FTM_MODE_FAULTM_MASK (0x3<<5)
|
|
||||||
|
|
||||||
#define PWM_K64_FTM_MODE_FAULTIE (0x1<<7)
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_SYNC PWM Synchronization */
|
|
||||||
#define PWM_K64_FTM_SYNC_CNTMIN (0x1<<0)
|
|
||||||
#define PWM_K64_FTM_SYNC_CNTMAX (0x1<<1)
|
|
||||||
#define PWM_K64_FTM_SYNC_REINIT (0x1<<2)
|
|
||||||
#define PWM_K64_FTM_SYNC_SYNCHOM (0x1<<3)
|
|
||||||
#define PWM_K64_FTM_SYNC_TRIG0 (0x1<<4)
|
|
||||||
#define PWM_K64_FTM_SYNC_TRIG1 (0x1<<5)
|
|
||||||
#define PWM_K64_FTM_SYNC_TRIG2 (0x1<<6)
|
|
||||||
#define PWM_K64_FTM_SYNC_SWSYNC (0x1<<7)
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_EXTTRIG FTM External Trigger */
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_CH2TRIG (0x1<<0)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_CH3TRIG (0x1<<1)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_CH4TRIG (0x1<<2)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_CH5TRIG (0x1<<3)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_CH0TRIG (0x1<<4)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_CH1TRIG (0x1<<5)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_INTTRIGEN (0x1<<6)
|
|
||||||
#define PWM_K64_FTM_EXTTRIG_TRIGF (0x1<<7)
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_QDCTRL Quadrature Decoder Ctrl&Status */
|
|
||||||
#define PWM_K64_FTM_QDCTRL_QUADEN (0x1<<0)
|
|
||||||
|
|
||||||
/* PWM_K64_FTM_SYNCONF Syncronization Configuration */
|
|
||||||
#define PWM_K64_FTM_SYNCONF_HWTRIGMODE (0x1<<0)
|
|
||||||
#define PWM_K64_FTM_SYNCONF_CNTINC (0x1<<2)
|
|
||||||
#define PWM_K64_FTM_SYNCONF_INVC (0x1<<4)
|
|
||||||
#define PWM_K64_FTM_SYNCONF_SWOC (0x1<<5)
|
|
||||||
#define PWM_K64_FTM_SYNCONF_SYNCMODE (0x1<<7)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initialization function for FlexTimer Module FTM (PWM mode)
|
|
||||||
*
|
|
||||||
* @param dev Device struct
|
|
||||||
* @return 0 if successful, failed otherwise
|
|
||||||
*/
|
|
||||||
extern int pwm_ftm_init(struct device *dev);
|
|
||||||
|
|
||||||
/** Configuration data */
|
|
||||||
struct pwm_ftm_config {
|
|
||||||
|
|
||||||
/* FTM register base address */
|
|
||||||
u32_t ftm_num;
|
|
||||||
|
|
||||||
/* FTM register base address */
|
|
||||||
u32_t reg_base;
|
|
||||||
|
|
||||||
/* FTM prescale (1,2,4,8,16,32,64,128) */
|
|
||||||
u32_t prescale;
|
|
||||||
|
|
||||||
/* FTM clock source */
|
|
||||||
u32_t clock_source;
|
|
||||||
|
|
||||||
/* If phase is not 0, the odd-numbered channel is not available */
|
|
||||||
bool phase_enable0; /* combine pwm0, pwm1 for phase capability */
|
|
||||||
bool phase_enable2; /* combine pwm2, pwm3 for phase capability */
|
|
||||||
bool phase_enable4; /* combine pwm4, pwm4 for phase capability */
|
|
||||||
bool phase_enable6; /* combine pwm6, pwm5 for phase capability */
|
|
||||||
|
|
||||||
/* FTM period (clock ticks) */
|
|
||||||
u32_t period;
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
/** Runtime driver data */
|
|
||||||
struct pwm_ftm_drv_data {
|
|
||||||
u32_t phase[4];
|
|
||||||
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
||||||
u32_t device_power_state;
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* __PWM_K64_FTM_H__ */
|
|
||||||
|
|
@ -1,206 +0,0 @@
|
||||||
/* Freescale K20 microprocessor SIM Module register definitions */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2013-2014 Wind River Systems, Inc.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SIM Registers Definitions for the K20 Microprocessor
|
|
||||||
*
|
|
||||||
* This module defines the SIM (System Integration Module) Registers for the
|
|
||||||
* K20 Family of microprocessors
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _K20SIM_H_
|
|
||||||
#define _K20SIM_H_
|
|
||||||
|
|
||||||
#include <zephyr/types.h>
|
|
||||||
#include <misc/__assert.h>
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define SIM_OCS32K_SYS 0
|
|
||||||
#define SIM_OCS32K_RTS 2
|
|
||||||
#define SIM_OCS32K_LPO 3 /* 1kHz */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value; /* reset = 0x8000 F03F */
|
|
||||||
struct {
|
|
||||||
u32_t res_0_11 : 12 __packed;
|
|
||||||
u32_t ram_size : 4 __packed;
|
|
||||||
u32_t res_16_17 : 2 __packed;
|
|
||||||
u32_t osc32k_sel : 2 __packed;
|
|
||||||
u32_t res_20_28 : 9 __packed;
|
|
||||||
u32_t usb_volt_stby : 1 __packed;
|
|
||||||
u32_t usb_stop_stby : 1 __packed;
|
|
||||||
u32_t usb_reg_en : 1 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SOPT1_t; /* 0x000 */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value;
|
|
||||||
struct {
|
|
||||||
u32_t res_0_23 : 24 __packed;
|
|
||||||
u32_t usb_reg_write_en : 1 __packed;
|
|
||||||
u32_t usb_volt_write_en : 1 __packed;
|
|
||||||
u32_t usb_stop_write_en : 1 __packed;
|
|
||||||
u32_t res_27_31 : 5 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SOPT1CFG_t; /* 0x004 */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value;
|
|
||||||
struct {
|
|
||||||
u32_t res_0_3 : 4 __packed;
|
|
||||||
u32_t rtc_clk_out_sel : 1 __packed;
|
|
||||||
u32_t clk_out_sel : 3 __packed;
|
|
||||||
u32_t flex_bus_sl : 2 __packed;
|
|
||||||
u32_t res_10 : 1 __packed;
|
|
||||||
u32_t ptd7pad : 1 __packed;
|
|
||||||
u32_t trace_clk_sel : 1 __packed;
|
|
||||||
u32_t res_13_15 : 3 __packed;
|
|
||||||
u32_t fll_pll_clk_sel : 1 __packed;
|
|
||||||
u32_t res_17 : 1 __packed;
|
|
||||||
u32_t usb_src : 1 __packed;
|
|
||||||
u32_t res_19_31 : 13 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SOPT2_t; /* 0x1004 */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value;
|
|
||||||
struct {
|
|
||||||
u32_t ftm0_flt0 : 1 __packed;
|
|
||||||
u32_t ftm0_flt1 : 1 __packed;
|
|
||||||
u32_t ftm0_flt2 : 1 __packed;
|
|
||||||
u32_t res_3 : 1 __packed;
|
|
||||||
u32_t ftm1_flt0 : 1 __packed;
|
|
||||||
u32_t res_5_7 : 3 __packed;
|
|
||||||
u32_t ftm2_flt0 : 1 __packed;
|
|
||||||
u32_t res_9_17 : 9 __packed;
|
|
||||||
u32_t ftm1_ch0_src : 2 __packed;
|
|
||||||
u32_t ftm2_ch0_src : 2 __packed;
|
|
||||||
u32_t res_22_23 : 2 __packed;
|
|
||||||
u32_t ftm0_clk_sel : 1 __packed;
|
|
||||||
u32_t ftm1_clk_sel : 1 __packed;
|
|
||||||
u32_t ftm2_clk_sel : 1 __packed;
|
|
||||||
u32_t res_27 : 1 __packed;
|
|
||||||
u32_t ftm0_trg0_src : 1 __packed;
|
|
||||||
u32_t ftm0_trg1_src : 1 __packed;
|
|
||||||
u32_t res_30_31 : 2 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SOPT4_t; /* 0x100C */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value;
|
|
||||||
struct {
|
|
||||||
u32_t uart0_tx_src : 2 __packed;
|
|
||||||
u32_t uart0_rx_src : 2 __packed;
|
|
||||||
u32_t uart1_tx_src : 2 __packed;
|
|
||||||
u32_t uart1_rx_src : 2 __packed;
|
|
||||||
u32_t res_8_31 : 24 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SOPT5_t; /* 0x1010 */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value;
|
|
||||||
struct {
|
|
||||||
u32_t uart0_tx_src : 2 __packed;
|
|
||||||
u32_t uart0_rx_src : 2 __packed;
|
|
||||||
u32_t uart1_tx_src : 2 __packed;
|
|
||||||
u32_t uart1_rx_src : 2 __packed;
|
|
||||||
u32_t res_8_9 : 2 __packed;
|
|
||||||
u32_t uart4_clk_en : 1 __packed;
|
|
||||||
u32_t uart5_clk_en : 1 __packed;
|
|
||||||
u32_t res_12_31: 20 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SCGC1_t; /* 0x1028*/
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value;
|
|
||||||
struct {
|
|
||||||
u32_t res_0 : 1 __packed;
|
|
||||||
u32_t ewm_clk_en_0 : 1 __packed;
|
|
||||||
u32_t cmt_clk_en_0 : 1 __packed;
|
|
||||||
u32_t res_3_5 : 3 __packed;
|
|
||||||
u32_t i2c0_clk_en : 1 __packed;
|
|
||||||
u32_t i2c1_clk_en : 1 __packed;
|
|
||||||
u32_t res_8_9 : 2 __packed;
|
|
||||||
u32_t uart0_clk_en : 1 __packed;
|
|
||||||
u32_t uart1_clk_en : 1 __packed;
|
|
||||||
u32_t uart2_clk_en : 1 __packed;
|
|
||||||
u32_t uart3_clk_en : 1 __packed;
|
|
||||||
u32_t res_14_17 : 4 __packed;
|
|
||||||
u32_t usb_clk_en : 1 __packed;
|
|
||||||
u32_t cmp_clk_en : 1 __packed;
|
|
||||||
u32_t vref_clk_en : 1 __packed;
|
|
||||||
u32_t res_21_31 : 11 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SCGC4_t; /* 0x1034 */
|
|
||||||
|
|
||||||
#define SIM_SCGC5_PORTA_CLK_EN (1 << 9)
|
|
||||||
#define SIM_SCGC5_PORTB_CLK_EN (1 << 10)
|
|
||||||
#define SIM_SCGC5_PORTC_CLK_EN (1 << 11)
|
|
||||||
#define SIM_SCGC5_PORTD_CLK_EN (1 << 12)
|
|
||||||
#define SIM_SCGC5_PORTE_CLK_EN (1 << 13)
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value; /* reset 0 */
|
|
||||||
struct {
|
|
||||||
u32_t lptimer : 1 __packed;
|
|
||||||
u32_t res_1_4 : 4 __packed;
|
|
||||||
u32_t tsi : 1 __packed;
|
|
||||||
u32_t res_6_8 : 3 __packed;
|
|
||||||
u32_t port_a_clk_en : 1 __packed;
|
|
||||||
u32_t port_b_clk_en : 1 __packed;
|
|
||||||
u32_t port_c_clk_en : 1 __packed;
|
|
||||||
u32_t port_d_clk_en : 1 __packed;
|
|
||||||
u32_t port_e_clk_en : 1 __packed;
|
|
||||||
u32_t res_14_31 : 18 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_SCGC5_t; /* 0x1038 */
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
u32_t value; /* reset 0x0001 0000 */
|
|
||||||
struct {
|
|
||||||
u32_t res_0_15 : 16 __packed;
|
|
||||||
u32_t outdiv4 : 4 __packed;
|
|
||||||
u32_t outdiv3 : 4 __packed;
|
|
||||||
u32_t outdiv2 : 4 __packed;
|
|
||||||
u32_t outdiv1 : 4 __packed;
|
|
||||||
} field;
|
|
||||||
} SIM_CLKDIV1_t; /* 0x1044 */
|
|
||||||
|
|
||||||
/* K20 Microntroller SIM module register structure */
|
|
||||||
|
|
||||||
struct K20_SIM {
|
|
||||||
SIM_SOPT1_t sopt1; /* 0x0000 */
|
|
||||||
SIM_SOPT1CFG_t sopt1_cfg; /* 0x0004 */
|
|
||||||
u8_t res0008_1003[0x1003 - 0x8]; /* 0x0008-0x1003 Reserved */
|
|
||||||
SIM_SOPT2_t sopt2; /* 0x1004 */
|
|
||||||
u32_t res1008; /* 0x1008 Reserved */
|
|
||||||
SIM_SOPT4_t sopt4; /* 0x100C */
|
|
||||||
SIM_SOPT5_t sopt5; /* 0x1010 */
|
|
||||||
u32_t res1014; /* 0x1014 Reserved */
|
|
||||||
u32_t sopt7; /* 0x1018 */
|
|
||||||
u8_t res101c_1027[0x1027 - 0x101c]; /* Reserved */
|
|
||||||
SIM_SCGC1_t scgc1; /* 0x1028 */
|
|
||||||
u32_t scgc2; /* 0x102C */
|
|
||||||
u32_t scgc3; /* 0x1030 */
|
|
||||||
SIM_SCGC4_t scgc4; /* 0x1034 */
|
|
||||||
SIM_SCGC5_t scgc5; /* 0x1038 */
|
|
||||||
u32_t scgc6; /* 0x103C */
|
|
||||||
u32_t scgc7; /* 0x1040 */
|
|
||||||
SIM_CLKDIV1_t clkdiv1; /* 0x1044 */
|
|
||||||
u32_t clkdiv2; /* 0x1048 */
|
|
||||||
u8_t res104c_1063[0x1063 - 0x104c]; /* Reserved */
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _K20SIM_H_ */
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue