From 45e55d639d5d96436cc4cba87ed7d9fbb5f4f2bc Mon Sep 17 00:00:00 2001 From: Michael Hope Date: Sat, 24 May 2025 15:52:37 +0000 Subject: [PATCH] drivers: pwm: fix an off-by-one error in the CH32V PWM driver The period is the reload register plus 1. Adjust. Note that the earlier code handles the cases where the pulse time is zero or equal to the period. Signed-off-by: Michael Hope --- drivers/pwm/pwm_wch_gptm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm_wch_gptm.c b/drivers/pwm/pwm_wch_gptm.c index 26f70a9af7e..46fa4b52a9e 100644 --- a/drivers/pwm/pwm_wch_gptm.c +++ b/drivers/pwm/pwm_wch_gptm.c @@ -94,7 +94,11 @@ static int pwm_wch_gptm_set_cycles(const struct device *dev, uint32_t channel, } if (period_cycles != 0) { - regs->ATRLR = period_cycles; + /* + * Note that the period is ATRLR+1. The earlier checks handle the case where + * pulse_cycles is zero or equal to period_cycles. + */ + regs->ATRLR = period_cycles - 1; } /* Set the polarity and enable */