drivers: Add MAX32690 clock control driver
Clock control for MAX32690 Co-authored-by: Okan Sahin <okan.sahin@analog.com> Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
This commit is contained in:
parent
e0528e3852
commit
45df8963f1
7 changed files with 329 additions and 0 deletions
36
dts/bindings/clock/adi,max32-gcr.yaml
Normal file
36
dts/bindings/clock/adi,max32-gcr.yaml
Normal file
|
@ -0,0 +1,36 @@
|
|||
# Copyright (c) 2023-2024 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: MAX32 Global Control
|
||||
|
||||
compatible: "adi,max32-gcr"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
sysclk-prescaler:
|
||||
type: int
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
- 64
|
||||
- 128
|
||||
|
||||
description: |
|
||||
SYSCLK prescaler. Defines actual core clock frequency SYSCLK
|
||||
based on system frequency input. Some MAX32xxx devices does not
|
||||
support this feature, check your device user guide before using it.
|
||||
|
||||
clock-cells:
|
||||
- offset
|
||||
- bit
|
Loading…
Add table
Add a link
Reference in a new issue