From 45b6aa4c3b5c569c9216467fa5e40220f78e6cf0 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Thu, 16 Dec 2021 11:54:51 +0800 Subject: [PATCH] ITE: drivers/i2c: add the compatibility of GPIO F2/F3 for i2c3 The default I2C channel 3 is used by alternate function of GPIO H1/H2 Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the compatibility of the GPIO F2/F3. TEST=test on it8xxx2_evb: zmake configure -b zephyr/projects/it8xxx2_evb/ Signed-off-by: Tim Lin --- drivers/i2c/i2c_ite_it8xxx2.c | 25 +++------------------- drivers/pinmux/pinmux_ite_it8xxx2.c | 10 ++++++++- dts/riscv/it8xxx2-alts-map.dtsi | 10 +++++++-- dts/riscv/it8xxx2.dtsi | 4 ++-- soc/riscv/riscv-ite/common/chip_chipregs.h | 7 ++++++ 5 files changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/i2c/i2c_ite_it8xxx2.c b/drivers/i2c/i2c_ite_it8xxx2.c index e8cec68c28f..2d52cb2c4fb 100644 --- a/drivers/i2c/i2c_ite_it8xxx2.c +++ b/drivers/i2c/i2c_ite_it8xxx2.c @@ -148,22 +148,6 @@ enum i2c_reset_cause { #define I2C_LINE_SDA_HIGH BIT(1) #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH) -struct i2c_pin { - volatile uint8_t *mirror_clk; - volatile uint8_t *mirror_data; - uint8_t clk_mask; - uint8_t data_mask; -}; - -static const struct i2c_pin i2c_pin_regs[] = { - { &GPDMRB, &GPDMRB, 0x08, 0x10}, - { &GPDMRC, &GPDMRC, 0x02, 0x04}, - { &GPDMRF, &GPDMRF, 0x40, 0x80}, - { &GPDMRH, &GPDMRH, 0x02, 0x04}, - { &GPDMRE, &GPDMRE, 0x01, 0x80}, - { &GPDMRA, &GPDMRA, 0x10, 0x20}, -}; - static int i2c_parsing_return_value(const struct device *dev) { struct i2c_it8xxx2_data *data = DEV_DATA(dev); @@ -201,12 +185,11 @@ static int i2c_get_line_levels(const struct device *dev) return IT83XX_SMB_SMBPCTL(base) & 0x03; } - if (*i2c_pin_regs[config->port].mirror_clk & - i2c_pin_regs[config->port].clk_mask) { + if (IT83XX_I2C_TOS(base) & IT8XXX2_I2C_SCL_IN) { pin_sts |= I2C_LINE_SCL_HIGH; } - if (*i2c_pin_regs[config->port].mirror_data & - i2c_pin_regs[config->port].data_mask) { + + if (IT83XX_I2C_TOS(base) & IT8XXX2_I2C_SDA_IN) { pin_sts |= I2C_LINE_SDA_HIGH; } @@ -905,8 +888,6 @@ static int i2c_it8xxx2_init(const struct device *dev) break; case DT_REG_ADDR(DT_NODELABEL(i2c3)): offset = CGC_OFFSET_SMBD; - /* Enable SMBus D channel */ - GCR2 |= SMB3E; break; case DT_REG_ADDR(DT_NODELABEL(i2c4)): offset = CGC_OFFSET_SMBE; diff --git a/drivers/pinmux/pinmux_ite_it8xxx2.c b/drivers/pinmux/pinmux_ite_it8xxx2.c index 8305823a0bc..8da8375129b 100644 --- a/drivers/pinmux/pinmux_ite_it8xxx2.c +++ b/drivers/pinmux/pinmux_ite_it8xxx2.c @@ -162,10 +162,18 @@ static int pinmux_it8xxx2_init(const struct device *dev) IT8XXX2_GPIO_GCR &= ~(BIT(1) | BIT(2)); /* - * TODO: If SMBUS3 swaps from H group to F group, we have to + * If SMBUS3 swaps from H group to F group, we have to * set SMB3PSEL = 1 in PMER3 register. */ + if (DEVICE_DT_GET(DT_PHANDLE(DT_NODELABEL(i2c3), gpio_dev)) == + DEVICE_DT_GET(DT_NODELABEL(gpiof))) { + struct gctrl_it8xxx2_regs *const gctrl_base = + (struct gctrl_it8xxx2_regs *) + DT_REG_ADDR(DT_NODELABEL(gctrl)); + + gctrl_base->GCTRL_PMER3 |= IT8XXX2_GCTRL_SMB3PSEL; + } /* * TODO: If UART2 swaps from bit2:1 to bit6:5 in H group, we * have to set UART1PSEL = 1 in UART1PMR register. diff --git a/dts/riscv/it8xxx2-alts-map.dtsi b/dts/riscv/it8xxx2-alts-map.dtsi index 3b0943b4207..21cd39e8cae 100644 --- a/dts/riscv/it8xxx2-alts-map.dtsi +++ b/dts/riscv/it8xxx2-alts-map.dtsi @@ -95,12 +95,18 @@ pinctrl_i2c_data2: i2c_data2 { pinctrls = <&pinmuxf 7 IT8XXX2_PINMUX_FUNC_1>; }; - pinctrl_i2c_clk3: i2c_clk3 { + pinctrl_i2c_clk3_gph1: i2c_clk3_gph1 { pinctrls = <&pinmuxh 1 IT8XXX2_PINMUX_FUNC_3>; }; - pinctrl_i2c_data3: i2c_data3 { + pinctrl_i2c_data3_gph2: i2c_data3_gph2 { pinctrls = <&pinmuxh 2 IT8XXX2_PINMUX_FUNC_3>; }; + pinctrl_i2c_clk3_gpf2: i2c_clk3_gpf2 { + pinctrls = <&pinmuxf 2 IT8XXX2_PINMUX_FUNC_4>; + }; + pinctrl_i2c_data3_gpf3: i2c_data3_gpf3 { + pinctrls = <&pinmuxf 3 IT8XXX2_PINMUX_FUNC_4>; + }; pinctrl_i2c_clk4: i2c_clk4 { pinctrls = <&pinmuxe 0 IT8XXX2_PINMUX_FUNC_3>; }; diff --git a/dts/riscv/it8xxx2.dtsi b/dts/riscv/it8xxx2.dtsi index e3bc49e3554..20777af31bc 100644 --- a/dts/riscv/it8xxx2.dtsi +++ b/dts/riscv/it8xxx2.dtsi @@ -707,8 +707,8 @@ label = "I2C_3"; port-num = <3>; gpio-dev = <&gpioh>; - pinctrl-0 = <&pinctrl_i2c_clk3 /* GPH1 */ - &pinctrl_i2c_data3>; /* GPH2 */ + pinctrl-0 = <&pinctrl_i2c_clk3_gph1 /* GPH1 */ + &pinctrl_i2c_data3_gph2>; /* GPH2 */ }; i2c4: i2c@f03500 { compatible = "ite,it8xxx2-i2c"; diff --git a/soc/riscv/riscv-ite/common/chip_chipregs.h b/soc/riscv/riscv-ite/common/chip_chipregs.h index ec9b9785ea9..eeff0b79ba9 100644 --- a/soc/riscv/riscv-ite/common/chip_chipregs.h +++ b/soc/riscv/riscv-ite/common/chip_chipregs.h @@ -1652,6 +1652,11 @@ enum chip_pll_mode { #define IT83XX_I2C_RAMH2A(base) ECREG(base+0x50) #define IT83XX_I2C_CMD_ADDH2(base) ECREG(base+0x52) +/* SMBus/I2C register fields */ +/* 0x07: Time Out Status */ +#define IT8XXX2_I2C_SCL_IN BIT(2) +#define IT8XXX2_I2C_SDA_IN BIT(0) + /* --- General Control (GCTRL) --- */ #define IT83XX_GCTRL_BASE 0x00F02000 @@ -1847,6 +1852,8 @@ struct gctrl_it8xxx2_regs { #define IT8XXX2_GCTRL_LRSIWR BIT(2) #define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1) #define IT8XXX2_GCTRL_LRSIPGWR BIT(0) +/* 0x46: Pin Multi-function Enable 3 */ +#define IT8XXX2_GCTRL_SMB3PSEL BIT(6) /* 0x4B: ETWD and UART Control */ #define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0) /* Accept Port 80h Cycle */