arm: cmsis: Introduce CMSIS layer

Support using CMSIS defines and functions, we either pull the expect
defines/enum from the SoC HAL layers via <soc.h> for the SoC or we
provide a default set based on __NVIC_PRIO_BITS is defined.

We provide defaults in the case for:
	IRQn_Type enum
	*_REV define (set to 0)
	__MPU_PRESENT define (set to 0 - no MPU)
	__NVIC_PRIO_BITS define (set to CONFIG_NUM_IRQ_PRIO_BITS)
	__Vendor_SysTickConfig (set to 0 - standard SysTick)

Jira: ZEP-1568

Change-Id: Ibc203de79f4697b14849b69c0e8c5c43677b5c6e
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

arch/arm/core/Kconfig

@@ -19,6 +19,7 @@ config CPU_CORTEX_M
 	default n
 	select CPU_CORTEX
 	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select HAS_CMSIS
 	help
 	This option signifies the use of a CPU of the Cortex-M family.
 

arch/arm/core/cortex_m/Makefile

@@ -1,6 +1,7 @@
 ccflags-y +=-I$(srctree)/include/drivers
 ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
 ccflags-y +=-I$(srctree)/kernel/include
+ccflags-y +=-I$(srctree)/include/
 
 asflags-y = $(ccflags-y)
 

arch/arm/soc/nxp_kinetis/k6x/soc.h

@@ -134,6 +134,7 @@ extern "C" {
 
 #ifndef _ASMLANGUAGE
 
+#include <fsl_common.h>
 #include <device.h>
 #include <misc/util.h>
 #include <drivers/rand32.h>

include/arch/arm/cortex_m/cmsis.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2017 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief CMSIS interface file
+ *
+ * This header contains the interface to the ARM CMSIS Core headers.
+ */
+
+#ifndef _CMSIS__H_
+#define _CMSIS__H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <soc.h>
+
+/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
+ * Use __NVIC_PRIO_BITS as it is required and simple to check, but
+ * ultimately all SoCs will define their own CMSIS types and constants.
+ */
+#ifndef __NVIC_PRIO_BITS
+typedef enum {
+	Reset_IRQn                    = -15,
+	NonMaskableInt_IRQn           = -14,
+	HardFault_IRQn                = -13,
+#if defined(CONFIG_ARMV7_M)
+	MemoryManagement_IRQn         = -12,
+	BusFault_IRQn                 = -11,
+	UsageFault_IRQn               = -10,
+#endif /* CONFIG_ARMV7_M */
+	SVCall_IRQn                   =  -5,
+	DebugMonitor_IRQn             =  -4,
+	PendSV_IRQn                   =  -2,
+	SysTick_IRQn                  =  -1,
+} IRQn_Type;
+
+#if defined(CONFIG_CPU_CORTEX_M0)
+#define __CM0_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
+#define __CM0PLUS_REV    0
+#elif defined(CONFIG_CPU_CORTEX_M3)
+#define __CM3_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M4)
+#define __CM4_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M7)
+#define __CM7_REV        0
+#else
+#error "Uknown Cortex-M device"
+#endif
+
+#define __MPU_PRESENT                  0 /* Zephyr has no MPU support */
+#define __NVIC_PRIO_BITS               CONFIG_NUM_IRQ_PRIO_BITS
+#define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
+#endif /* __NVIC_PRIO_BITS */
+
+#if defined(CONFIG_CPU_CORTEX_M0)
+#include <core_cm0.h>
+#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
+#include <core_cm0plus.h>
+#elif defined(CONFIG_CPU_CORTEX_M3)
+#include <core_cm3.h>
+#elif defined(CONFIG_CPU_CORTEX_M4)
+#include <core_cm4.h>
+#elif defined(CONFIG_CPU_CORTEX_M7)
+#include <core_cm7.h>
+#else
+#error "Uknown Cortex-M device"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CMSIS__H_ */