soc: intel_adsp: Add ACE soc series
ACE15_MTPM is one SOC from the ACE series. Organize it following cavs pattern. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
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26 changed files with 41 additions and 31 deletions
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@ -5,4 +5,4 @@
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config BOARD_INTEL_ADSP_ACE15_MTPM
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bool "Intel ADSP ACE 1.5 Meteor PCH M"
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depends on SOC_SERIES_INTEL_ACE1X
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depends on SOC_SERIES_INTEL_ACE
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@ -2,7 +2,8 @@
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_SOC_SERIES_INTEL_ACE1X=y
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CONFIG_SOC_SERIES_INTEL_ACE=y
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CONFIG_SOC_INTEL_ACE15_MTPM=y
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CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM=y
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CONFIG_GEN_ISR_TABLES=y
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@ -21,7 +21,7 @@ config DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP
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config DMA_INTEL_ADSP_GPDMA_HAS_LLP
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bool "Intel ADSP GPDMA Linear Link Position Feature"
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default y if SOC_SERIES_INTEL_ACE1X
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default y if SOC_SERIES_INTEL_ACE
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help
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Intel ADSP GPDMA may optionally have a linear link position
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feature.
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@ -188,7 +188,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev)
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uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
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uint32_t val;
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if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE1X)) {
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if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE)) {
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val = sys_read32(reg) | GPDMA_CTL_DGCD;
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} else {
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val = GPDMA_CTL_FDCGB;
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@ -197,7 +197,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev)
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sys_write32(val, reg);
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}
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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static void intel_adsp_gpdma_select_owner(const struct device *dev)
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{
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const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
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@ -228,7 +228,7 @@ int intel_adsp_gpdma_init(const struct device *dev)
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const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
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int ret;
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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/* Power up */
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ret = intel_adsp_gpdma_enable(dev);
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if (ret != 0) {
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@ -246,7 +246,7 @@ int intel_adsp_gpdma_init(const struct device *dev)
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/* Disable dynamic clock gating appropriately before initializing */
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intel_adsp_gpdma_clock_enable(dev);
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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/* DW DMA Owner Select to DSP */
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intel_adsp_gpdma_select_owner(dev);
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#endif
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@ -144,7 +144,7 @@ static uint32_t get_hpsram_bank_idx(uintptr_t pa)
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*/
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static uint16_t flags_to_tlb_perms(uint32_t flags)
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{
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
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uint16_t perms = 0;
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if ((flags & SYS_MM_MEM_PERM_RW) == SYS_MM_MEM_PERM_RW) {
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@ -161,7 +161,7 @@ static uint16_t flags_to_tlb_perms(uint32_t flags)
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#endif
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}
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
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/**
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* Convert TLB entry permission bits to the SYS_MM_MEM_PERM_* flags.
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*
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@ -186,7 +186,7 @@ static uint16_t tlb_perms_to_flags(uint16_t perms)
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static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking)
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{
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
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if (bank_idx > mtl_hpsram_get_bank_count()) {
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return -1;
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}
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@ -467,7 +467,7 @@ int sys_mm_drv_page_flag_get(void *virt, uint32_t *flags)
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ARG_UNUSED(virt);
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int ret = 0;
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
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#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
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uint16_t *tlb_entries = UINT_TO_POINTER(TLB_BASE);
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uint16_t ent;
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@ -12,7 +12,7 @@
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#include <cavs-idc.h>
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#include <adsp_shim.h>
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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#include <ace_v1x-regs.h>
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#endif
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@ -27,7 +27,7 @@
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#define COMPARATOR_IDX 0 /* 0 or 1 */
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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#define TIMER_IRQ MTL_IRQ_TO_ZEPHYR(MTL_INTL_TTS)
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#else
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#define TIMER_IRQ DSP_WCT_IRQ(COMPARATOR_IDX)
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@ -189,7 +189,7 @@ static void irq_init(void)
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* (for per-core control) above the interrupt controller.
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* Drivers need to do that part.
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*/
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1);
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*WCTCS |= ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX);
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#else
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@ -4,8 +4,8 @@
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(common)
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if(CONFIG_SOC_SERIES_INTEL_ACE1X)
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add_subdirectory(ace_v1x)
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if(CONFIG_SOC_SERIES_INTEL_ACE)
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add_subdirectory(ace)
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endif()
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if(CONFIG_INTEL_ADSP_CAVS)
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add_subdirectory(cavs)
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14
soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm
Normal file
14
soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm
Normal file
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@ -0,0 +1,14 @@
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_INTEL_ACE15_MTPM
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config SOC
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string
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default "intel_ace15_mtpm"
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config MP_NUM_CPUS
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default 3
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endif
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@ -1,23 +1,16 @@
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_INTEL_ACE1X
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if SOC_SERIES_INTEL_ACE
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config SOC_SERIES
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string
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default "ace_v1x"
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default "ace"
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config SOC_TOOLCHAIN_NAME
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string
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default "intel_s1000"
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config SOC
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string
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default "intel_ace15_mtpm"
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config MP_NUM_CPUS
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default 3
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config SMP
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default y
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@ -72,4 +65,6 @@ config LOG_BACKEND_ADSP
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endif # LOG
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endif # SOC_SERIES_INTEL_ACE1X
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source "soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*"
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endif # SOC_SERIES_INTEL_ACE
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@ -1,8 +1,8 @@
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_INTEL_ACE1X
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bool "Intel ACE 1.x"
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config SOC_SERIES_INTEL_ACE
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bool "Intel ACE"
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select SOC_FAMILY_INTEL_ADSP
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select XTENSA
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select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc-clang"))
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select SCHED_IPI_SUPPORTED
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select DW_ICTL_ACE_V1X
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help
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Intel ACE 1.x
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Intel ADSP ACE
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@ -6,6 +6,6 @@ choice
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config SOC_INTEL_ACE15_MTPM
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bool "ACE 1.5 Meteor PCH M"
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depends on SOC_SERIES_INTEL_ACE1X
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depends on SOC_SERIES_INTEL_ACE
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endchoice
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@ -42,7 +42,7 @@
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#define MANIFEST_SEGMENT_COUNT 3
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/* FIXME: Use Kconfig or some other means */
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#if !defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
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#if !defined(CONFIG_SOC_SERIES_INTEL_ACE)
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#define RESET_MEMORY_HOLE
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#endif
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