soc: intel_adsp: Add ACE soc series

ACE15_MTPM is one SOC from the ACE series. Organize
it following cavs pattern.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>

boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board

@@ -5,4 +5,4 @@
 
 config  BOARD_INTEL_ADSP_ACE15_MTPM
 	bool "Intel ADSP ACE 1.5 Meteor PCH M"
-	depends on SOC_SERIES_INTEL_ACE1X
+	depends on SOC_SERIES_INTEL_ACE

boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig

@@ -2,7 +2,8 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_ACE1X=y
+CONFIG_SOC_SERIES_INTEL_ACE=y
+CONFIG_SOC_INTEL_ACE15_MTPM=y
 CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM=y
 
 CONFIG_GEN_ISR_TABLES=y

drivers/dma/Kconfig.intel_adsp_gpdma

@@ -21,7 +21,7 @@ config DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP
 
 config DMA_INTEL_ADSP_GPDMA_HAS_LLP
 	bool "Intel ADSP GPDMA Linear Link Position Feature"
-	default y if SOC_SERIES_INTEL_ACE1X
+	default y if SOC_SERIES_INTEL_ACE
 	help
 	  Intel ADSP GPDMA may optionally have a linear link position
 	  feature.

drivers/dma/dma_intel_adsp_gpdma.c

@@ -188,7 +188,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev)
 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
 	uint32_t val;
 
-	if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE1X)) {
+	if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE)) {
 		val = sys_read32(reg) | GPDMA_CTL_DGCD;
 	} else {
 		val = GPDMA_CTL_FDCGB;
@@ -197,7 +197,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev)
 	sys_write32(val, reg);
 }
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
+#ifdef CONFIG_SOC_SERIES_INTEL_ACE
 static void intel_adsp_gpdma_select_owner(const struct device *dev)
 {
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
@@ -228,7 +228,7 @@ int intel_adsp_gpdma_init(const struct device *dev)
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
 	int ret;
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
+#ifdef CONFIG_SOC_SERIES_INTEL_ACE
 	/* Power up */
 	ret = intel_adsp_gpdma_enable(dev);
 	if (ret != 0) {
@@ -246,7 +246,7 @@ int intel_adsp_gpdma_init(const struct device *dev)
 	/* Disable dynamic clock gating appropriately before initializing */
 	intel_adsp_gpdma_clock_enable(dev);
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
+#ifdef CONFIG_SOC_SERIES_INTEL_ACE
 	/* DW DMA Owner Select to DSP */
 	intel_adsp_gpdma_select_owner(dev);
 #endif

drivers/mm/mm_drv_intel_adsp_mtl_tlb.c

@@ -144,7 +144,7 @@ static uint32_t get_hpsram_bank_idx(uintptr_t pa)
  */
 static uint16_t flags_to_tlb_perms(uint32_t flags)
 {
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
+#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
 	uint16_t perms = 0;
 
 	if ((flags & SYS_MM_MEM_PERM_RW) == SYS_MM_MEM_PERM_RW) {
@@ -161,7 +161,7 @@ static uint16_t flags_to_tlb_perms(uint32_t flags)
 #endif
 }
 
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
+#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
 /**
  * Convert TLB entry permission bits to the SYS_MM_MEM_PERM_* flags.
  *
@@ -186,7 +186,7 @@ static uint16_t tlb_perms_to_flags(uint16_t perms)
 
 static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking)
 {
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
+#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
 	if (bank_idx > mtl_hpsram_get_bank_count()) {
 		return -1;
 	}
@@ -467,7 +467,7 @@ int sys_mm_drv_page_flag_get(void *virt, uint32_t *flags)
 	ARG_UNUSED(virt);
 	int ret = 0;
 
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
+#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
 	uint16_t *tlb_entries = UINT_TO_POINTER(TLB_BASE);
 	uint16_t ent;
 

drivers/timer/intel_adsp_timer.c

@@ -12,7 +12,7 @@
 #include <cavs-idc.h>
 #include <adsp_shim.h>
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
+#ifdef CONFIG_SOC_SERIES_INTEL_ACE
 #include <ace_v1x-regs.h>
 #endif
 
@@ -27,7 +27,7 @@
 
 #define COMPARATOR_IDX  0 /* 0 or 1 */
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
+#ifdef CONFIG_SOC_SERIES_INTEL_ACE
 #define TIMER_IRQ MTL_IRQ_TO_ZEPHYR(MTL_INTL_TTS)
 #else
 #define TIMER_IRQ DSP_WCT_IRQ(COMPARATOR_IDX)
@@ -189,7 +189,7 @@ static void irq_init(void)
 	 * (for per-core control) above the interrupt controller.
 	 * Drivers need to do that part.
 	 */
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
+#ifdef CONFIG_SOC_SERIES_INTEL_ACE
 	MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1);
 	*WCTCS |= ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX);
 #else

soc/xtensa/intel_adsp/CMakeLists.txt

@@ -4,8 +4,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 add_subdirectory(common)
-if(CONFIG_SOC_SERIES_INTEL_ACE1X)
+if(CONFIG_SOC_SERIES_INTEL_ACE)
-	add_subdirectory(ace_v1x)
+	add_subdirectory(ace)
 endif()
 if(CONFIG_INTEL_ADSP_CAVS)
 	add_subdirectory(cavs)

soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm

@@ -0,0 +1,14 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+if SOC_INTEL_ACE15_MTPM
+
+config SOC
+	string
+	default "intel_ace15_mtpm"
+
+config MP_NUM_CPUS
+	default 3
+
+endif

soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series

@@ -1,23 +1,16 @@
 # Copyright (c) 2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_ACE1X
+if SOC_SERIES_INTEL_ACE
 
 config SOC_SERIES
 	string
-	default "ace_v1x"
+	default "ace"
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_s1000"
 
-config SOC
-	string
-	default "intel_ace15_mtpm"
-
-config MP_NUM_CPUS
-	default 3
-
 config SMP
 	default y
 
@@ -72,4 +65,6 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif # SOC_SERIES_INTEL_ACE1X
+source "soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*"
+
+endif # SOC_SERIES_INTEL_ACE

soc/xtensa/intel_adsp/ace/Kconfig.series

@@ -1,8 +1,8 @@
 # Copyright (c) 2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_INTEL_ACE1X
+config SOC_SERIES_INTEL_ACE
-	bool "Intel ACE 1.x"
+	bool "Intel ACE"
 	select SOC_FAMILY_INTEL_ADSP
 	select XTENSA
 	select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc-clang"))
@@ -11,4 +11,4 @@ config SOC_SERIES_INTEL_ACE1X
 	select SCHED_IPI_SUPPORTED
 	select DW_ICTL_ACE_V1X
 	help
-	  Intel ACE 1.x
+	  Intel ADSP ACE

soc/xtensa/intel_adsp/ace/Kconfig.soc

@@ -6,6 +6,6 @@ choice
 
 	config SOC_INTEL_ACE15_MTPM
 		bool "ACE 1.5 Meteor PCH M"
-		depends on SOC_SERIES_INTEL_ACE1X
+		depends on SOC_SERIES_INTEL_ACE
 
 endchoice

soc/xtensa/intel_adsp/common/boot.c

@@ -42,7 +42,7 @@
 #define MANIFEST_SEGMENT_COUNT	3
 
 /* FIXME: Use Kconfig or some other means */
-#if !defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
+#if !defined(CONFIG_SOC_SERIES_INTEL_ACE)
 #define RESET_MEMORY_HOLE
 #endif