From 44bfd32f22128113d16f094d1216704700ce7fb7 Mon Sep 17 00:00:00 2001 From: Daniel Wagenknecht Date: Sun, 28 Jan 2018 02:28:49 +0100 Subject: [PATCH] dts: spi: add remaining SPI fixup defines for STM32 Add SPI fixup defines on STM32 SoC family level for all SPIs that are supported on one or more SOCs of that SoC family. Signed-off-by: Daniel Wagenknecht --- arch/arm/soc/st_stm32/stm32f0/dts.fixup | 5 +++++ arch/arm/soc/st_stm32/stm32f1/dts.fixup | 18 +++++++++++++---- arch/arm/soc/st_stm32/stm32f3/dts.fixup | 26 +++++++++++++++++-------- arch/arm/soc/st_stm32/stm32f4/dts.fixup | 20 +++++++++++++++++++ arch/arm/soc/st_stm32/stm32l4/dts.fixup | 5 +++++ 5 files changed, 62 insertions(+), 12 deletions(-) diff --git a/arch/arm/soc/st_stm32/stm32f0/dts.fixup b/arch/arm/soc/st_stm32/stm32f0/dts.fixup index e299e26269e..bab0ea4c5af 100644 --- a/arch/arm/soc/st_stm32/stm32f0/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f0/dts.fixup @@ -31,6 +31,11 @@ #define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL #define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0 +#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS +#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY +#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL +#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0 + #define FLASH_DEV_BASE_ADDRESS ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0 #define FLASH_DEV_NAME ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL diff --git a/arch/arm/soc/st_stm32/stm32f1/dts.fixup b/arch/arm/soc/st_stm32/stm32f1/dts.fixup index c52acd94b2a..e7cd34ae0cc 100644 --- a/arch/arm/soc/st_stm32/stm32f1/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f1/dts.fixup @@ -28,9 +28,19 @@ #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY -#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS -#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL -#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0 +#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS +#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY +#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL +#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0 + +#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS +#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY +#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL +#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0 + +#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS +#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY +#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL +#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0 /* End of SoC Level DTS fixup file */ diff --git a/arch/arm/soc/st_stm32/stm32f3/dts.fixup b/arch/arm/soc/st_stm32/stm32f3/dts.fixup index cfa3b5756ae..31d3263128e 100644 --- a/arch/arm/soc/st_stm32/stm32f3/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f3/dts.fixup @@ -30,15 +30,25 @@ #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY -#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS -#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL -#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0 +#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS +#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY +#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL +#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS -#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY -#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL -#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0 +#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS +#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY +#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL +#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0 + +#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS +#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY +#define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL +#define CONFIG_SPI_3_IRQ ST_STM32_SPI_FIFO_40003C00_IRQ_0 + +#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS +#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY +#define CONFIG_SPI_4_NAME ST_STM32_SPI_FIFO_40013C00_LABEL +#define CONFIG_SPI_4_IRQ ST_STM32_SPI_FIFO_40013C00_IRQ_0 #define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0 #define FLASH_DEV_NAME ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL diff --git a/arch/arm/soc/st_stm32/stm32f4/dts.fixup b/arch/arm/soc/st_stm32/stm32f4/dts.fixup index 948fe66fff1..e05b4374374 100644 --- a/arch/arm/soc/st_stm32/stm32f4/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f4/dts.fixup @@ -60,6 +60,26 @@ #define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL #define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0 +#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS +#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY +#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL +#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0 + +#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_40013400_BASE_ADDRESS +#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_40013400_IRQ_0_PRIORITY +#define CONFIG_SPI_4_NAME ST_STM32_SPI_40013400_LABEL +#define CONFIG_SPI_4_IRQ ST_STM32_SPI_40013400_IRQ_0 + +#define CONFIG_SPI_5_BASE_ADDRESS ST_STM32_SPI_40015000_BASE_ADDRESS +#define CONFIG_SPI_5_IRQ_PRI ST_STM32_SPI_40015000_IRQ_0_PRIORITY +#define CONFIG_SPI_5_NAME ST_STM32_SPI_40015000_LABEL +#define CONFIG_SPI_5_IRQ ST_STM32_SPI_40015000_IRQ_0 + +#define CONFIG_SPI_6_BASE_ADDRESS ST_STM32_SPI_40015400_BASE_ADDRESS +#define CONFIG_SPI_6_IRQ_PRI ST_STM32_SPI_40015400_IRQ_0_PRIORITY +#define CONFIG_SPI_6_NAME ST_STM32_SPI_40015400_LABEL +#define CONFIG_SPI_6_IRQ ST_STM32_SPI_40015400_IRQ_0 + #define FLASH_DEV_BASE_ADDRESS ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS_0 #define FLASH_DEV_NAME ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL diff --git a/arch/arm/soc/st_stm32/stm32l4/dts.fixup b/arch/arm/soc/st_stm32/stm32l4/dts.fixup index 1fd7fdf4ba9..a559e21d846 100644 --- a/arch/arm/soc/st_stm32/stm32l4/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32l4/dts.fixup @@ -53,6 +53,11 @@ #define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL #define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0 +#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS +#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY +#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL +#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0 + #define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS #define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL