From 44bf4a124b3f318586251f7207fbfad4da1869c8 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 5 Jan 2021 12:07:38 +0100 Subject: [PATCH] cavs: (cosmetic) remove redundant LPRAM_* macros LPRAM_BASE and LPRAM_SIZE are duplicates of LP_SRAM_BASE and LP_SRAM_SIZE respectively. Remove them and use LP_SRAM_* consistently everywhere. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v15/linker.ld | 8 ++++---- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v18/linker.ld | 8 ++++---- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v20/linker.ld | 8 ++++---- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 10 +++------- soc/xtensa/intel_adsp/cavs_v25/linker.ld | 9 +++++---- 8 files changed, 32 insertions(+), 35 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 2bfb93f66a4..f0560ad1483 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -92,10 +92,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - /* bootloader */ #define HP_SRAM_BASE 0xbe000000 @@ -215,4 +211,8 @@ /* Host page size */ #define HOST_PAGE_SIZE 4096 +/* low power ram where DMA buffers are typically placed */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) + #endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index 8586340c06f..dd27ba428c3 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -25,7 +25,7 @@ OUTPUT_ARCH(xtensa) PROVIDE(__memctl_default = 0x00000000); PROVIDE(_MemErrorHandler = 0x00000000); -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram /* DSP RAM regions (all of them) are mapped twice on the DSP: once in * a 512MB region from 0x80000000-0x9fffffff and again from @@ -123,8 +123,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -509,7 +509,7 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 8e10613d11f..a927ca63107 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -89,10 +89,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - /* bootloader */ #define HP_SRAM_BASE 0xbe000000 @@ -217,4 +213,8 @@ #define SRAM_BANK_SIZE (64 * 1024) +/* low power ram where DMA buffers are typically placed */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) + #endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld index e0141e203fc..e62de5c0edc 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld @@ -27,7 +27,7 @@ PROVIDE(_MemErrorHandler = 0x00000000); #define RAMABLE_REGION ram :ram_phdr #define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram MEMORY { @@ -103,8 +103,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -474,7 +474,7 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 58e44e4f3b2..5a22e712e1b 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -89,10 +89,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - /* bootloader */ #define HP_SRAM_BASE 0xbe000000 @@ -221,4 +217,8 @@ #define SRAM_BANK_SIZE (64 * 1024) +/* low power ram where DMA buffers are typically placed */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) + #endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld index b144b121039..d7152189115 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld @@ -27,7 +27,7 @@ PROVIDE(_MemErrorHandler = 0x00000000); #define RAMABLE_REGION ram :ram_phdr #define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram MEMORY { @@ -103,8 +103,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -473,7 +473,7 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 8b5a59b25e2..d2e01928480 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -89,9 +89,6 @@ /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) #define SRAM_BANK_SIZE (64 * 1024) /* bootloader */ @@ -220,10 +217,9 @@ /* Host page size */ #define HOST_PAGE_SIZE 4096 -/* LP SRAM */ -#define LP_SRAM_BASE 0xBE800000 - -#define LP_SRAM_SIZE (0x10000 * 2) +/* low power RAM where DMA buffers are typically placed, used by linker.ld */ +#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) /* alternate reset vector */ #define LP_SRAM_ALT_RESET_VEC_BASE LP_SRAM_BASE diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index a5c7cb46ea5..dd47c82d8e9 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -27,7 +27,7 @@ PROVIDE(_MemErrorHandler = 0x00000000); #define RAMABLE_REGION ram :ram_phdr #define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram +#define LP_SRAM_REGION lpram MEMORY { @@ -103,8 +103,8 @@ MEMORY len = IDT_SIZE #endif lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE + org = LP_SRAM_BASE, + len = LP_SRAM_SIZE static_uuid_entries_seg (!ari) : org = UUID_ENTRY_ELF_BASE, @@ -542,7 +542,8 @@ SECTIONS _dma_buf_start = ABSOLUTE(.); *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION + } >LP_SRAM_REGION + _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) }