test: mpu: Add arm_mpu_regions test

A a test for the new DT-configured memory regions.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

tests/misc/arm_mpu_regions/CMakeLists.txt

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+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(arm_mpu_regions)
+
+target_sources(app PRIVATE src/main.c)

tests/misc/arm_mpu_regions/boards/mps2_an385.overlay

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+/*
+ * Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	/delete-node/ memory@20000000;
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x200000>;
+	};
+
+	sram_cache: memory@20200000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20200000 0x100000>;
+		zephyr,memory-region = "SRAM_CACHE";
+		zephyr,memory-region-mpu = "RAM";
+	};
+
+	sram_no_cache: memory@20300000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20300000 0x100000>;
+		zephyr,memory-region = "SRAM_NO_CACHE";
+		zephyr,memory-region-mpu = "RAM_NOCACHE";
+	};
+
+	sram_dtcm_fake: memory@abcdabcd {
+		compatible = "zephyr,memory-region", "arm,dtcm";
+		reg = <0xabcdabcd 0x100000>;
+		zephyr,memory-region = "SRAM_DTCM_FAKE";
+		zephyr,memory-region-mpu = "RAM";
+	};
+
+	sram_no_mpu: memory@deaddead {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xdeaddead 0x100000>;
+		zephyr,memory-region = "SRAM_NO_MPU";
+	};
+};

tests/misc/arm_mpu_regions/prj.conf

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+CONFIG_ZTEST=y

tests/misc/arm_mpu_regions/src/main.c

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+/*
+ * Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include <linker/linker-defs.h>
+#include <sys/slist.h>
+#include <arch/arm/aarch32/mpu/arm_mpu.h>
+#include <ztest.h>
+#include <string.h>
+
+extern const struct arm_mpu_config mpu_config;
+
+static arm_mpu_region_attr_t cacheable = REGION_RAM_ATTR(REGION_1M);
+static arm_mpu_region_attr_t noncacheable = REGION_RAM_NOCACHE_ATTR(REGION_1M);
+
+static void test_regions(void)
+{
+	int cnt = 0;
+
+	for (size_t i = 0; i < mpu_config.num_regions; i++) {
+		const struct arm_mpu_region *r = &mpu_config.mpu_regions[i];
+
+		if (!strcmp(r->name, "SRAM_CACHE")) {
+			zassert_equal(r->base, 0x20200000, "Wrong base");
+			zassert_equal(r->attr.rasr, cacheable.rasr,
+				      "Wrong attr for SRAM_CACHE");
+			cnt++;
+		} else if (!strcmp(r->name, "SRAM_NO_CACHE")) {
+			zassert_equal(r->base, 0x20300000, "Wrong base");
+			zassert_equal(r->attr.rasr, noncacheable.rasr,
+				      "Wrong attr for SRAM_NO_CACHE");
+			cnt++;
+		} else if (!strcmp(r->name, "SRAM_DTCM_FAKE")) {
+			zassert_equal(r->base, 0xabcdabcd, "Wrong base");
+			zassert_equal(r->attr.rasr, cacheable.rasr,
+				      "Wrong attr for SRAM_DTCM_FAKE");
+			cnt++;
+		}
+	}
+
+	if (cnt != 3) {
+		/*
+		 * SRAM0 and SRAM_NO_MPU should not create any MPU region.
+		 * Check that.
+		 */
+		ztest_test_fail();
+	}
+}
+
+void test_main(void)
+{
+	ztest_test_suite(test_c_arm_mpu_regions,
+			ztest_unit_test(test_regions)
+			);
+
+	ztest_run_test_suite(test_c_arm_mpu_regions);
+}

tests/misc/arm_mpu_regions/testcase.yaml

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+tests:
+  misc.arm_mpu_regions:
+    platform_allow: mps2_an385
+    tags: sample board sram mpu