diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi
index 1edd8e9acaf..f17281b973d 100644
--- a/dts/arm/st/l1/stm32l1.dtsi
+++ b/dts/arm/st/l1/stm32l1.dtsi
@@ -25,6 +25,33 @@
 	};
 
 	soc {
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
 		rcc: rcc@40023800 {
 			compatible = "st,stm32-rcc";
 			clocks-controller;
diff --git a/soc/arm/st_stm32/stm32l1/dts_fixup.h b/soc/arm/st_stm32/stm32l1/dts_fixup.h
index c24a56ddac1..8e09623b300 100644
--- a/soc/arm/st_stm32/stm32l1/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32l1/dts_fixup.h
@@ -8,4 +8,31 @@
 
 #define DT_NUM_IRQ_PRIO_BITS	        DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
 
+#define DT_UART_STM32_USART_1_BASE_ADDRESS	DT_ST_STM32_USART_40013800_BASE_ADDRESS
+#define DT_UART_STM32_USART_1_BAUD_RATE	DT_ST_STM32_USART_40013800_CURRENT_SPEED
+#define DT_UART_STM32_USART_1_IRQ_PRI	DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define DT_UART_STM32_USART_1_NAME		DT_ST_STM32_USART_40013800_LABEL
+#define DT_USART_1_IRQ				DT_ST_STM32_USART_40013800_IRQ_0
+#define DT_UART_STM32_USART_1_CLOCK_BITS	DT_ST_STM32_USART_40013800_CLOCK_BITS
+#define DT_UART_STM32_USART_1_CLOCK_BUS	DT_ST_STM32_USART_40013800_CLOCK_BUS
+#define DT_UART_STM32_USART_1_HW_FLOW_CONTROL DT_ST_STM32_USART_40013800_HW_FLOW_CONTROL
+
+#define DT_UART_STM32_USART_2_BASE_ADDRESS	DT_ST_STM32_USART_40004400_BASE_ADDRESS
+#define DT_UART_STM32_USART_2_BAUD_RATE	DT_ST_STM32_USART_40004400_CURRENT_SPEED
+#define DT_UART_STM32_USART_2_IRQ_PRI	DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define DT_UART_STM32_USART_2_NAME		DT_ST_STM32_USART_40004400_LABEL
+#define DT_USART_2_IRQ				DT_ST_STM32_USART_40004400_IRQ_0
+#define DT_UART_STM32_USART_2_CLOCK_BITS	DT_ST_STM32_USART_40004400_CLOCK_BITS
+#define DT_UART_STM32_USART_2_CLOCK_BUS	DT_ST_STM32_USART_40004400_CLOCK_BUS
+#define DT_UART_STM32_USART_2_HW_FLOW_CONTROL DT_ST_STM32_USART_40004400_HW_FLOW_CONTROL
+
+#define DT_UART_STM32_USART_3_BASE_ADDRESS	DT_ST_STM32_USART_40004800_BASE_ADDRESS
+#define DT_UART_STM32_USART_3_BAUD_RATE	DT_ST_STM32_USART_40004800_CURRENT_SPEED
+#define DT_UART_STM32_USART_3_IRQ_PRI	DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define DT_UART_STM32_USART_3_NAME		DT_ST_STM32_USART_40004800_LABEL
+#define DT_USART_3_IRQ				DT_ST_STM32_USART_40004800_IRQ_0
+#define DT_UART_STM32_USART_3_CLOCK_BITS	DT_ST_STM32_USART_40004800_CLOCK_BITS
+#define DT_UART_STM32_USART_3_CLOCK_BUS	DT_ST_STM32_USART_40004800_CLOCK_BUS
+#define DT_UART_STM32_USART_3_HW_FLOW_CONTROL DT_ST_STM32_USART_40004800_HW_FLOW_CONTROL
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32l1/soc.h b/soc/arm/st_stm32/stm32l1/soc.h
index 68c44226f7e..5f39b9cb042 100644
--- a/soc/arm/st_stm32/stm32l1/soc.h
+++ b/soc/arm/st_stm32/stm32l1/soc.h
@@ -35,6 +35,10 @@
 #include <stm32l1xx_ll_rcc.h>
 #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32l1xx_ll_usart.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32L1_SOC_H_ */