soc: espressif: Simple boot support
Add simplistic booting method which allows to load without 2nd stage bootloader. Update common architecture loader to support all build scenarios. - simple boot: using single binary application without bootloader - mcuboot: zephyr port of MCUboot - application: loaded by the MCUboot Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej
Anas Nashif
parent
7236321743
commit
43e3088c2d
2 changed files with 152 additions and 34 deletions
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@ -127,4 +127,12 @@ config SPI_FLASH_HPM_ENABLE
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This option is invisible, and will be selected automatically
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when ``ESPTOOLPY_FLASHFREQ_120M`` is selected.
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config ESP_SIMPLE_BOOT
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bool "Simple Boot method"
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default y if !BOOTLOADER_MCUBOOT
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help
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The Simple Boot is a method of booting that doesn't depend on a
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2nd stage bootloader. Please note that some of the bootloader features
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are not available using simple boot, such secure boot and OTA.
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endif # SOC_FAMILY_ESPRESSIF_ESP32
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,24 +12,59 @@
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#include <hal/cache_hal.h>
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#include <rom/cache.h>
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#include <esp_rom_sys.h>
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#include <esp_err.h>
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#define MMU_FLASH_MASK (~(CONFIG_MMU_PAGE_SIZE - 1))
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#include <esp_app_format.h>
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#include <zephyr/storage/flash_map.h>
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#include "esp_rom_uart.h"
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#include "esp_flash.h"
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#include "esp_log.h"
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#include "bootloader_init.h"
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#define TAG "boot"
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#define CHECKSUM_ALIGN 16
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#define IS_PADD(addr) (addr == 0)
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#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
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#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
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#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
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#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
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#define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
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#define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
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#define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
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&& !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr))
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#define BOOT_LOG_INF(_fmt, ...) \
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ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
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#define BOOT_LOG_ERR(_fmt, ...) \
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ets_printf("[" CONFIG_SOC_SERIES "] [ERR] " _fmt "\n\r", ##__VA_ARGS__)
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#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
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void __start(void);
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static HDR_ATTR void (*_entry_point)(void) = &__start;
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extern esp_image_header_t bootloader_image_hdr;
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extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
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extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
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static uint32_t _app_irom_start = (FIXED_PARTITION_OFFSET(slot0_partition) +
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(uint32_t)&_image_irom_start);
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static uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
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static uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr);
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static uint32_t _app_drom_start = (FIXED_PARTITION_OFFSET(slot0_partition) +
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(uint32_t)&_image_drom_start);
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static uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
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static uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr);
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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static esp_err_t spi_flash_read(uint32_t address, void *buffer, size_t length)
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{
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return esp_flash_read(NULL, buffer, address, length);
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}
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
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@ -43,12 +78,74 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
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uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
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uint32_t actual_mapped_len = 0;
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
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size_t offset = FIXED_PARTITION_OFFSET(boot_partition);
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bool checksum = false;
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unsigned int segments = 0;
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unsigned int ram_segments = 0;
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/* Using already fetched bootloader image header from bootloader_init */
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offset += sizeof(esp_image_header_t);
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while (segments++ < 16) {
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if (spi_flash_read(offset, &segment_hdr,
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sizeof(esp_image_segment_header_t)) != ESP_OK) {
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BOOT_LOG_ERR("Failed to read segment header at %x", offset);
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abort();
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}
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/* TODO: Find better end-of-segment detection */
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if (IS_NONE(segment_hdr.load_addr)) {
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/* Total segment count = (segments - 1) */
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break;
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}
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BOOT_LOG_INF("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)",
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IS_NONE(segment_hdr.load_addr) ? "???" :
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IS_MMAP(segment_hdr.load_addr) ?
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IS_IROM(segment_hdr.load_addr) ? "IMAP" : "DMAP" :
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IS_PADD(segment_hdr.load_addr) ? "padd" :
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IS_DRAM(segment_hdr.load_addr) ? "DRAM" : "IRAM",
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offset + sizeof(esp_image_segment_header_t),
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segment_hdr.load_addr, segment_hdr.data_len, segment_hdr.data_len);
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/* Fix drom and irom produced be the linker, as it could
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* be invalidated by the elf2image and flash load offset
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*/
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if (segment_hdr.load_addr == _app_drom_vaddr) {
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app_drom_start = offset + sizeof(esp_image_segment_header_t);
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app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
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}
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if (segment_hdr.load_addr == _app_irom_vaddr) {
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app_irom_start = offset + sizeof(esp_image_segment_header_t);
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app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
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}
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if (IS_SRAM(segment_hdr.load_addr)) {
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ram_segments++;
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}
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offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len;
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if (ram_segments == bootloader_image_hdr.segment_count && !checksum) {
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offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1;
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checksum = true;
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}
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}
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if (segments == 0 || segments == 16) {
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BOOT_LOG_ERR("Error parsing segments");
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abort();
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}
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BOOT_LOG_INF("Image with %d segments", segments - 1);
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#endif /* !CONFIG_BOOTLOADER_MCUBOOT */
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#if CONFIG_SOC_SERIES_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#else
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cache_hal_disable(CACHE_TYPE_ALL);
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#endif
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#endif /* CONFIG_SOC_SERIES_ESP32 */
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/* Clear the MMU entries that are already set up,
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* so the new app only has the mappings it creates.
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@ -73,16 +170,18 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
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rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned,
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app_irom_start_aligned, 64, irom_page_count);
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if (rc != 0) {
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esp_rom_printf("Failed to setup XIP, aborting\n");
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BOOT_LOG_ERR("Failed to setup XIP, aborting");
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abort();
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}
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#else
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mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned,
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mmu_hal_map_region(0, MMU_TARGET_FLASH0,
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app_drom_vaddr_aligned, app_drom_start_aligned,
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app_drom_size, &actual_mapped_len);
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mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned,
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mmu_hal_map_region(0, MMU_TARGET_FLASH0,
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app_irom_vaddr_aligned, app_irom_start_aligned,
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app_irom_size, &actual_mapped_len);
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#endif
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#endif /* CONFIG_SOC_SERIES_ESP32 */
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/* ----------------------Enable corresponding buses---------------- */
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size);
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@ -103,31 +202,42 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
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Cache_Read_Enable(0);
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#else
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cache_hal_enable(CACHE_TYPE_ALL);
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#endif
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#endif /* CONFIG_SOC_SERIES_ESP32 */
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/* Show map segments continue using same log format as during MCUboot phase */
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BOOT_LOG_INF("DROM segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map",
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app_drom_start_aligned, app_drom_vaddr_aligned,
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app_drom_size, app_drom_size);
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BOOT_LOG_INF("IROM segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map\r\n",
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app_irom_start_aligned, app_irom_vaddr_aligned,
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app_irom_size, app_irom_size);
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esp_rom_uart_tx_wait_idle(0);
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}
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void __start(void)
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{
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
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uint32_t _app_irom_start = (_partition_offset + (uint32_t)&_image_irom_start);
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uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
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uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr);
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#ifdef CONFIG_RISCV_GP
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/* Configure the global pointer register
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* (This should be the first thing startup does, as any other piece of code could be
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* relaxed by the linker to access something relative to __global_pointer$)
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*/
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__asm__ __volatile__(".option push\n"
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop");
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#endif /* CONFIG_RISCV_GP */
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uint32_t _app_drom_start = (_partition_offset + (uint32_t)&_image_drom_start);
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uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
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uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr);
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uint32_t actual_mapped_len = 0;
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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/* Init fundamental components */
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if (bootloader_init()) {
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BOOT_LOG_ERR("HW init failed, aborting");
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abort();
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}
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#endif
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#ifndef CONFIG_MCUBOOT
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map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size,
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_app_irom_start, _app_irom_vaddr, _app_irom_size);
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/* Show map segments continue using same log format as during MCUboot phase */
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BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
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_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
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BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
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_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
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esp_rom_uart_tx_wait_idle(0);
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#endif
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__esp_platform_start();
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}
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