drivers: mspi: Add Ambiq apollo3p mspi controller

The Ambiq MSPI controller is implemented using the MSPI bus API.
The hardware supports up to 48MHz octal SDR with XIP, scrambling and
hardware command queue features.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>

boards/ambiq/apollo3p_evb/apollo3p_evb.yaml

@@ -14,6 +14,7 @@ supported:
   - gpio
   - spi
   - i2c
+  - mspi
 testing:
   ignore_tags:
     - net

drivers/mspi/CMakeLists.txt

@@ -3,4 +3,5 @@
 zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/mspi.h)
 
 zephyr_library()
+zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ_AP3   mspi_ambiq_ap3.c)
 zephyr_library_sources_ifdef(CONFIG_MSPI_EMUL        mspi_emul.c)

drivers/mspi/Kconfig

@@ -59,6 +59,7 @@ module = MSPI
 module-str = mspi
 source "subsys/logging/Kconfig.template.log_config"
 
+source "drivers/mspi/Kconfig.ambiq"
 source "drivers/mspi/Kconfig.mspi_emul"
 
 endif # MSPI

drivers/mspi/Kconfig.ambiq

@@ -0,0 +1,28 @@
+# Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config MSPI_AMBIQ_AP3
+	bool "Ambiq Apollo3 series MSPI driver"
+	default y
+	depends on DT_HAS_AMBIQ_MSPI_CONTROLLER_ENABLED
+	select AMBIQ_HAL
+	select AMBIQ_HAL_USE_MSPI
+	select MSPI_XIP
+	select MSPI_SCRAMBLE
+	select MSPI_TIMING
+	select GPIO
+	help
+	  Enable driver for Ambiq MSPI.
+
+config MSPI_AMBIQ_BUFF_RAM_LOCATION
+	hex "byte offset to SRAM_BASE_ADDRESS"
+	default 0x50000
+	help
+	  This option specifies the mspi buffer/heap start address
+
+config MSPI_AMBIQ_BUFF_ALIGNMENT
+	int "byte alignment of the MSPI buffer"
+	default 8 if MSPI_AMBIQ_AP3
+	default 4
+	help
+	  This option specifies the mspi buffer alignment

drivers/mspi/mspi_ambiq.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef MSPI_AMBIQ_H_
+#define MSPI_AMBIQ_H_
+
+#include <am_mcu_apollo.h>
+
+/* Hand-calculated minimum heap sizes needed to return a successful
+ * 1-byte allocation.  See details in lib/os/heap.[ch]
+ */
+#define MSPI_AMBIQ_HEAP_MIN_SIZE (sizeof(void *) > 4 ? 56 : 44)
+
+#define MSPI_AMBIQ_HEAP_DEFINE(name, bytes)                                                       \
+	char __attribute__((section(".mspi_buff")))                                               \
+		kheap_##name[MAX(bytes, MSPI_AMBIQ_HEAP_MIN_SIZE)];                               \
+	STRUCT_SECTION_ITERABLE(k_heap, name) = {                                                 \
+		.heap =                                                                           \
+			{                                                                         \
+				.init_mem = kheap_##name,                                         \
+				.init_bytes = MAX(bytes, MSPI_AMBIQ_HEAP_MIN_SIZE),               \
+			},                                                                        \
+	}
+
+struct mspi_ambiq_timing_cfg {
+	uint8_t ui8WriteLatency;
+	uint8_t ui8TurnAround;
+	bool bTxNeg;
+	bool bRxNeg;
+	bool bRxCap;
+	uint32_t ui32TxDQSDelay;
+	uint32_t ui32RxDQSDelay;
+	uint32_t ui32RXDQSDelayEXT;
+};
+
+enum mspi_ambiq_timing_param {
+	MSPI_AMBIQ_SET_WLC            = BIT(0),
+	MSPI_AMBIQ_SET_RLC            = BIT(1),
+	MSPI_AMBIQ_SET_TXNEG          = BIT(2),
+	MSPI_AMBIQ_SET_RXNEG          = BIT(3),
+	MSPI_AMBIQ_SET_RXCAP          = BIT(4),
+	MSPI_AMBIQ_SET_TXDQSDLY       = BIT(5),
+	MSPI_AMBIQ_SET_RXDQSDLY       = BIT(6),
+	MSPI_AMBIQ_SET_RXDQSDLYEXT    = BIT(7),
+};
+
+#define TIMING_CFG_GET_RX_DUMMY(cfg)                                                              \
+	{                                                                                         \
+		mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg;                                 \
+		timing->ui8TurnAround;                                                            \
+	}
+
+#define TIMING_CFG_SET_RX_DUMMY(cfg, num)                                                         \
+	{                                                                                         \
+		mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg;                                 \
+		timing->ui8TurnAround = num;                                                      \
+	}
+
+#endif

west.yml

@@ -147,7 +147,7 @@ manifest:
       groups:
         - hal
     - name: hal_ambiq
-      revision: fcbbd99e20db1432196f4aec92678bd1f5b19c96
+      revision: 367ae6a0396e3074bebbd55ef72f8e577168e567
       path: modules/hal/ambiq
       groups:
         - hal