diff --git a/boards/riscv/litex_vexriscv/doc/index.rst b/boards/riscv/litex_vexriscv/doc/index.rst
index df4071c88f1..cf9b63f6cf6 100644
--- a/boards/riscv/litex_vexriscv/doc/index.rst
+++ b/boards/riscv/litex_vexriscv/doc/index.rst
@@ -43,9 +43,6 @@ The implementation is optimized for FPGA chips.
 More information about the project can be found on
 `VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
 
-LiteX VexRiscv
-##############
-
 To run the ZephyrOS on the VexRiscv CPU, it is necessary to prepare the
 bitstream for the FPGA on a Digilent Arty A7-35 Board. This can be achieved
 using the