samples: kernel: add cycle64 sample

The cycle64 sample is intended to complement
`test_clock_cycle_64()` in `tests/kernel/common`.

The sample demonstrates the upper 32-bits of the 64-bit cycle
counter incrementing when the bottom 32-bits roll over from
`UINT32_MAX` to 0.

If the upper 32-bits of the 64-bit cycle counter does not
increment, then an error message is printed.

```
west build -p auto -b qemu_cortex_a53 -t run \
	samples/kernel/cycle64
...
*** Booting Zephyr OS build v2.7.99-1124-gd7ba4e394832  ***
wrap-around should occur in 68s
[ddd:hh:mm:ss.0ms]
[000:00:00:00.020]: c64: 0000000000174258
[000:00:01:08.760]: c64: 000000010027f8bb
[000:00:02:17.490]: c64: 0000000200348c85
```

Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>

samples/kernel/cycle64/CMakeLists.txt

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(cycle64)
+
+FILE(GLOB app_sources src/main.c)
+target_sources(app PRIVATE ${app_sources})

samples/kernel/cycle64/prj.conf

@@ -0,0 +1,3 @@
+CONFIG_TEST=y
+CONFIG_PRINTK=y
+CONFIG_ASSERT=y

samples/kernel/cycle64/sample.yaml

@@ -0,0 +1,17 @@
+sample:
+  description: k_cycle_get_64() example
+  name: cycle64
+common:
+  integration_platforms:
+    - native_posix_64
+    - qemu_riscv
+    - qemu_riscv64
+  tags: kernel
+  harness: console
+  harness_config:
+    type: one_line
+    regex:
+      - "SUCCESS"
+tests:
+    sample.kernel.cycle64:
+        filter: CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER

samples/kernel/cycle64/src/main.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021 Friedt Professional Engineering Services, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+static void swap64(uint64_t *a, uint64_t *b)
+{
+	uint64_t t = *a;
+	*a = *b;
+	*b = t;
+}
+
+static void msg(uint64_t c64)
+{
+	int64_t ms = k_uptime_get();
+	int s = ms / 1000;
+	int m = s / 60;
+	int h = m / 60;
+	int d = h / 24;
+
+	h %= 24;
+	m %= 60;
+	s %= 60;
+	ms %= 1000;
+
+	printk("[%03d:%02d:%02d:%02d.%03d]: cycle: %016" PRIx64 "\n", d, h, m, s, (int)ms, c64);
+}
+
+uint32_t timeout(uint64_t prev, uint64_t now)
+{
+	uint64_t next = prev + BIT64(32) - now;
+
+	next &= UINT32_MAX;
+	if (next == 0) {
+		next = UINT32_MAX;
+	}
+
+	return (uint32_t)next;
+}
+
+void main(void)
+{
+	enum {
+		CURR,
+		PREV,
+	};
+
+	int i;
+	uint64_t now;
+	uint64_t c64[2];
+
+	printk("wrap-around should occur in %us\n",
+	       (uint32_t)(BIT64(32) / (uint32_t)sys_clock_hw_cycles_per_sec()));
+
+	printk("[ddd:hh:mm:ss.0ms]\n");
+
+	c64[CURR] = k_cycle_get_64();
+	msg(c64[CURR]);
+
+	for (i = 0; i < 3; ++i) {
+		k_sleep(Z_TIMEOUT_CYC(timeout(c64[CURR], k_cycle_get_64())));
+
+		now = k_cycle_get_64();
+		swap64(&c64[PREV], &c64[CURR]);
+		c64[CURR] = now;
+
+		msg(c64[CURR]);
+
+		__ASSERT(((c64[CURR] - c64[PREV]) >> 32) == 1,
+			 "The 64-bit cycle counter did not increment!");
+	}
+
+	printk("SUCCESS\n");
+}