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drivers: mbox: nxp_s32: use instance-based DT macros

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At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-11-09 18:00:57 +07:00 • committed by Anas Nashif
commit 434a40470c
2 changed files with 44 additions and 57 deletions
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10
soc/arm/nxp_s32/s32ze/soc.h
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@ -51,4 +51,14 @@
/* NETC */
#define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE
/* MRU */
#define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE
#define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE
#define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE
#define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE
#define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE
#define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE
#define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE
#define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE
#endif /* _NXP_S32_S32ZE_SOC_H_ */