soc: arm: nxp_imx: add rt117x support
1. Added RT10xx and RT11xx configs 2. Added a new soc file for rt117x. There are clock differences between the RT10xx and RT11xx series, hence the soc files have been separated. Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
This commit is contained in:
Ryan QIAN
Anas Nashif
parent
2883d727a7
commit
431345ae79
9 changed files with 625 additions and 17 deletions
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@ -56,6 +56,8 @@
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#define REGION_SRAM_SIZE REGION_4M
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#elif CONFIG_SRAM_SIZE == 32768
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#define REGION_SRAM_SIZE REGION_32M
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#elif CONFIG_SRAM_SIZE == 65536
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#define REGION_SRAM_SIZE REGION_64M
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#else
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#error "Unsupported sram size configuration"
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#endif
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@ -1,12 +1,10 @@
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#
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# Copyright (c) 2017, NXP
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# Copyright (c) 2017-2021, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX soc_rt11xx.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c)
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zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER
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ROM_START SORT_KEY 0 boot_header.ld)
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17
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4
Normal file
17
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4
Normal file
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@ -0,0 +1,17 @@
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# i.MX RT1170 CM4
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# Copyright (c) 2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MIMXRT1176_CM4
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config SOC
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default "mimxrt1176_cm4"
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config NUM_IRQS
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default 218
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config GPIO
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default y
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endif # SOC_MIMXRT1170_CM4
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17
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7
Normal file
17
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7
Normal file
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@ -0,0 +1,17 @@
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# i.MX RT1170 CM7
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# Copyright (c) 2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MIMXRT1176_CM7
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config SOC
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default "mimxrt1176_cm7"
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config NUM_IRQS
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default 218
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config GPIO
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default y
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endif # SOC_MIMXRT1176_CM7
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@ -1,6 +1,6 @@
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# i.MX RT series
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# Copyright (c) 2017, NXP
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# Copyright (c) 2017-2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_IMX_RT
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@ -20,6 +20,10 @@ config CLOCK_CONTROL_MCUX_CCM
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default y if HAS_MCUX_CCM
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depends on CLOCK_CONTROL
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config CLOCK_CONTROL_MCUX_CCM_REV2
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default y if HAS_MCUX_CCM_REV2
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depends on CLOCK_CONTROL
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config DISPLAY_MCUX_ELCDIF
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default y if HAS_MCUX_ELCDIF
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depends on DISPLAY
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@ -76,30 +80,47 @@ endif # CODE_SEMC
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if CODE_ITCM
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config FLASH_SIZE
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default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K)
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default $(dt_node_reg_size_int,/soc/flexram@40028000/itcm@0,0,K) if SOC_SERIES_IMX_RT11XX
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default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K) if SOC_SERIES_IMX_RT10XX
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/flexram@400b0000/itcm@0)
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default $(dt_node_reg_addr_hex,/soc/flexram@40028000/itcm@0) if SOC_SERIES_IMX_RT11XX
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default $(dt_node_reg_addr_hex,/soc/flexram@400b0000/itcm@0) if SOC_SERIES_IMX_RT10XX
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endif # CODE_ITCM
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if CODE_SRAM0
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config FLASH_SIZE
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default $(dt_node_reg_size_int,/soc/memory@1ffe0000,0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/memory@1ffe0000)
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endif # CODE_SRAM0
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if CODE_FLEXSPI
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config FLASH_SIZE
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default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K)
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default $(dt_node_reg_size_int,/soc/spi@400cc000,1,K) if SOC_SERIES_IMX_RT11XX
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default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K) if SOC_SERIES_IMX_RT10XX
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/spi@402a8000,1)
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default $(dt_node_reg_addr_hex,/soc/spi@400cc000,1) if SOC_SERIES_IMX_RT11XX
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default $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) if SOC_SERIES_IMX_RT10XX
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endif # CODE_FLEXSPI
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if CODE_FLEXSPI2
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config FLASH_SIZE
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default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K)
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default $(dt_node_reg_size_int,/soc/spi@4000d000,1,K) if SOC_SERIES_IMX_RT11XX
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default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K) if SOC_SERIES_IMX_RT10XX
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/spi@402a4000,1)
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default $(dt_node_reg_addr_hex,/soc/spi@4000d000,1) if SOC_SERIES_IMX_RT11XX
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default $(dt_node_reg_addr_hex,/soc/spi@402a4000,1) if SOC_SERIES_IMX_RT10XX
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endif # CODE_FLEXSPI2
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@ -1,13 +1,11 @@
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# iMX RT series
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# Copyright (c) 2017, NXP
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# Copyright (c) 2017-2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IMX_RT
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bool "i.MX RT Series"
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select ARM
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select CPU_CORTEX_M7
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select CPU_CORTEX_M_HAS_DWT
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select SOC_FAMILY_IMX
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select CLOCK_CONTROL
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help
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@ -1,6 +1,6 @@
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# i.MX RT series
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# Copyright (c) 2017-2020, NXP
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# Copyright (c) 2017-2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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choice
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@ -9,6 +9,7 @@ choice
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config SOC_MIMXRT1011
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bool "SOC_MIMXRT1011"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -30,6 +31,7 @@ config SOC_MIMXRT1011
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config SOC_MIMXRT1015
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bool "SOC_MIMXRT1015"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -52,6 +54,7 @@ config SOC_MIMXRT1015
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config SOC_MIMXRT1021
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bool "SOC_MIMXRT1021"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -77,6 +80,7 @@ config SOC_MIMXRT1021
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config SOC_MIMXRT1024
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bool "SOC_MIMXRT1024"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -101,6 +105,7 @@ config SOC_MIMXRT1024
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config SOC_MIMXRT1051
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bool "SOC_MIMXRT1051"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -127,6 +132,7 @@ config SOC_MIMXRT1051
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config SOC_MIMXRT1052
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bool "SOC_MIMXRT1052"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -157,6 +163,7 @@ config SOC_MIMXRT1052
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config SOC_MIMXRT1061
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bool "SOC_MIMXRT1061"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -183,6 +190,7 @@ config SOC_MIMXRT1061
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config SOC_MIMXRT1062
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bool "SOC_MIMXRT1062"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -213,6 +221,7 @@ config SOC_MIMXRT1062
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config SOC_MIMXRT1064
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bool "SOC_MIMXRT1064"
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select SOC_SERIES_IMX_RT10XX
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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@ -241,6 +250,48 @@ config SOC_MIMXRT1064
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select HAS_MCUX_EDMA
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select HAS_MCUX_FLEXCAN
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config SOC_MIMXRT1176_CM7
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bool "SOC_MIMXRT1176_CM7"
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select CPU_CORTEX_M7
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select CPU_CORTEX_M_HAS_DWT
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select SOC_SERIES_IMX_RT11XX
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select HAS_MCUX_CACHE
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select HAS_MCUX
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select HAS_MCUX_SEMC
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select HAS_MCUX_CCM_REV2
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPUART
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_ENET_PLL if NET_L2_ETHERNET
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select INIT_VIDEO_PLL
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select HAS_MCUX_EDMA
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select ADJUST_DCDC
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select BYPASS_LDO_LPSR
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select ADJUST_LDO
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config SOC_MIMXRT1176_CM4
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bool "SOC_MIMXRT1176_CM4"
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select CPU_CORTEX_M4
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select SOC_SERIES_IMX_RT11XX
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select HAS_MCUX_CACHE
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select HAS_MCUX
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select HAS_MCUX_SEMC
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select HAS_MCUX_CCM_REV2
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPUART
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select HAS_MCUX_GPT
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_ENET_PLL if NET_L2_ETHERNET
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select INIT_VIDEO_PLL
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select HAS_MCUX_EDMA
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endchoice
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if SOC_SERIES_IMX_RT
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@ -317,6 +368,45 @@ config SOC_PART_NUMBER_MIMXRT1064CVL5A
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config SOC_PART_NUMBER_MIMXRT1064DVL6A
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bool
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config SOC_PART_NUMBER_MIMXRT1176AVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1176CVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1176DVMAA
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bool
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config SOC_PART_NUMBER_MIMXRT1175AVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1175CVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1175DVMAA
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bool
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config SOC_PART_NUMBER_MIMXRT1173CVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1172AVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1172CVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1172DVMAA
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bool
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config SOC_PART_NUMBER_MIMXRT1171AVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1171CVM8A
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bool
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config SOC_PART_NUMBER_MIMXRT1171DVMAA
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bool
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config SOC_PART_NUMBER_IMX_RT
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string
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default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A
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@ -343,11 +433,32 @@ config SOC_PART_NUMBER_IMX_RT
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default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
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default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
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default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A
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default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A
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default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A
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default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA
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default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A
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default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A
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default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA
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default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A
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default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A
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default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A
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default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA
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default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A
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default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A
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default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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config SOC_SERIES_IMX_RT10XX
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bool "i.MX RT 10XX Series"
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select CPU_CORTEX_M7
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select CPU_CORTEX_M_HAS_DWT
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config SOC_SERIES_IMX_RT11XX
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bool "i.MX RT 11XX Series"
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config INIT_ARM_PLL
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bool "Initialize ARM PLL"
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@ -374,14 +485,26 @@ config HAS_ARM_DIV
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config ARM_DIV
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int "ARM clock divider"
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range 0 7
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default 0
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config AHB_DIV
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int "AHB clock divider"
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range 0 7
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default 0
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config IPG_DIV
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int "IPG clock divider"
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range 0 3
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default 0
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config ADJUST_DCDC
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bool "Adjust internal DCDC output"
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config BYPASS_LDO_LPSR
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bool "Bypass LDO lpsr"
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config ADJUST_LDO
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bool "Adjust LDO setting"
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menuconfig NXP_IMX_RT_BOOT_HEADER
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bool "Enable the boot header"
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@ -417,7 +540,7 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET
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FlexSPI configuration block consists of parameters regarding specific
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flash devices including read command sequence, quad mode enablement
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sequence (optional), etc. The boot ROM expectes FlexSPI configuration
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parameter to be presented in serail nor flash.
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parameter to be presented in serial nor flash.
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config IMAGE_VECTOR_TABLE_OFFSET
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hex "Image vector table offset"
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@ -455,6 +578,8 @@ config CODE_FLEXSPI2
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bool "Link code into internal FlexSPI-controlled memory"
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select NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
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config CODE_SRAM0
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bool "Link code into RAM_L memory (RAM_L)"
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endchoice
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endif # SOC_SERIES_IMX_RT
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430
soc/arm/nxp_imx/rt/soc_rt11xx.c
Normal file
430
soc/arm/nxp_imx/rt/soc_rt11xx.c
Normal file
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@ -0,0 +1,430 @@
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/*
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* Copyright (c) 2021, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <fsl_clock.h>
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#include <fsl_gpc.h>
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#include <fsl_pmu.h>
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#include <fsl_dcdc.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
|
||||
#include <fsl_flexspi_nor_boot.h>
|
||||
#if CONFIG_USB_DC_NXP_EHCI
|
||||
#include "usb_phy.h"
|
||||
#include "usb_dc_mcux.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_USB_DC_NXP_EHCI /* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x0CU)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_INIT_ARM_PLL
|
||||
static const clock_arm_pll_config_t armPllConfig = {
|
||||
/* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
|
||||
.postDivider = kCLOCK_PllPostDiv2,
|
||||
/* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
|
||||
.loopDivider = 166,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const clock_sys_pll2_config_t sysPll2Config = {
|
||||
/* Denominator of spread spectrum */
|
||||
.mfd = 268435455,
|
||||
/* Spread spectrum parameter */
|
||||
.ss = NULL,
|
||||
/* Enable spread spectrum or not */
|
||||
.ssEnable = false,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_INIT_ENET_PLL
|
||||
static const clock_sys_pll1_config_t sysPll1Config = {
|
||||
.pllDiv2En = true,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_INIT_VIDEO_PLL
|
||||
static const clock_video_pll_config_t videoPllConfig = {
|
||||
/* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
|
||||
.loopDivider = 41,
|
||||
/* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
|
||||
.postDivider = 0,
|
||||
/*
|
||||
* 30 bit numerator of fractional loop divider,
|
||||
* Fout = Fin * ( loopDivider + numerator / denominator )
|
||||
*/
|
||||
.numerator = 1,
|
||||
/*
|
||||
* 30 bit denominator of fractional loop divider,
|
||||
* Fout = Fin * ( loopDivider + numerator / denominator )
|
||||
*/
|
||||
.denominator = 960000,
|
||||
/* Spread spectrum parameter */
|
||||
.ss = NULL,
|
||||
/* Enable spread spectrum or not */
|
||||
.ssEnable = false,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if CONFIG_USB_DC_NXP_EHCI
|
||||
usb_phy_config_struct_t usbPhyConfig = {
|
||||
BOARD_USB_PHY_D_CAL,
|
||||
BOARD_USB_PHY_TXCAL45DP,
|
||||
BOARD_USB_PHY_TXCAL45DM,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
|
||||
const __imx_boot_data_section BOOT_DATA_T boot_data = {
|
||||
.start = CONFIG_FLASH_BASE_ADDRESS,
|
||||
.size = KB(CONFIG_FLASH_SIZE),
|
||||
.plugin = PLUGIN_FLAG,
|
||||
.placeholder = 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
extern char __start[];
|
||||
const __imx_boot_ivt_section ivt image_vector_table = {
|
||||
.hdr = IVT_HEADER,
|
||||
.entry = (uint32_t) __start,
|
||||
.reserved1 = IVT_RSVD,
|
||||
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
|
||||
.dcd = (uint32_t) dcd_data,
|
||||
#else
|
||||
.dcd = (uint32_t) NULL,
|
||||
#endif
|
||||
.boot_data = (uint32_t) &boot_data,
|
||||
.self = (uint32_t) &image_vector_table,
|
||||
.csf = (uint32_t)CSF_ADDRESS,
|
||||
.reserved2 = IVT_RSVD,
|
||||
};
|
||||
#endif
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Initialize the system clock
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
clock_root_config_t rootCfg = {0};
|
||||
|
||||
#if CONFIG_ADJUST_DCDC
|
||||
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
|
||||
#endif
|
||||
|
||||
/* Check if FBB need to be enabled in OverDrive(OD) mode */
|
||||
if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) {
|
||||
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
|
||||
} else {
|
||||
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
|
||||
}
|
||||
|
||||
#if CONFIG_BYPASS_LDO_LPSR
|
||||
PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
|
||||
PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
|
||||
#endif
|
||||
|
||||
#if CONFIG_ADJUST_LDO
|
||||
pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
|
||||
pmu_static_lpsr_dig_config_t lpsrDigConfig;
|
||||
|
||||
if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &
|
||||
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) {
|
||||
PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
|
||||
PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
|
||||
}
|
||||
|
||||
if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &
|
||||
ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) {
|
||||
PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
|
||||
lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
|
||||
PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* PLL LDO shall be enabled first before enable PLLs */
|
||||
|
||||
/* Config CLK_1M */
|
||||
CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
|
||||
|
||||
/* Init OSC RC 16M */
|
||||
ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
|
||||
|
||||
/* Init OSC RC 400M */
|
||||
CLOCK_OSC_EnableOscRc400M();
|
||||
CLOCK_OSC_GateOscRc400M(true);
|
||||
|
||||
/* Init OSC RC 48M */
|
||||
CLOCK_OSC_EnableOsc48M(true);
|
||||
CLOCK_OSC_EnableOsc48MDiv2(true);
|
||||
|
||||
/* Config OSC 24M */
|
||||
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) |
|
||||
ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) |
|
||||
ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) |
|
||||
ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) |
|
||||
ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
|
||||
|
||||
/* Wait for 24M OSC to be stable. */
|
||||
while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
|
||||
(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {
|
||||
}
|
||||
|
||||
/* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
|
||||
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
|
||||
#if CONFIG_SOC_MIMXRT1176_CM7
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_MIMXRT1176_CM4
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If DCD is used, please make sure the clock source of SEMC is not
|
||||
* changed in the following PLL/PFD configuration code.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_INIT_ARM_PLL
|
||||
/* Init Arm Pll. */
|
||||
CLOCK_InitArmPll(&armPllConfig);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_INIT_ENET_PLL
|
||||
CLOCK_InitSysPll1(&sysPll1Config);
|
||||
#else
|
||||
/* Bypass Sys Pll1. */
|
||||
CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
|
||||
|
||||
/* DeInit Sys Pll1. */
|
||||
CLOCK_DeinitSysPll1();
|
||||
#endif
|
||||
|
||||
/* Init Sys Pll2. */
|
||||
CLOCK_InitSysPll2(&sysPll2Config);
|
||||
|
||||
/* Init System Pll2 pfd0. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
|
||||
|
||||
/* Init System Pll2 pfd1. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
|
||||
|
||||
/* Init System Pll2 pfd2. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
|
||||
|
||||
/* Init System Pll2 pfd3. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
|
||||
|
||||
/* Init Sys Pll3. */
|
||||
CLOCK_InitSysPll3();
|
||||
|
||||
/* Init System Pll3 pfd0. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
|
||||
|
||||
/* Init System Pll3 pfd1. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
|
||||
|
||||
/* Init System Pll3 pfd2. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
|
||||
|
||||
/* Init System Pll3 pfd3. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
|
||||
|
||||
#ifdef CONFIG_INIT_VIDEO_PLL
|
||||
/* Init Video Pll. */
|
||||
CLOCK_InitVideoPll(&videoPllConfig);
|
||||
#endif
|
||||
|
||||
/* Module clock root configurations. */
|
||||
/* Configure M7 using ARM_PLL_CLK */
|
||||
#ifdef CONFIG_SOC_MIMXRT1176_CM7
|
||||
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure M4 using SYS_PLL3_PFD3_CLK */
|
||||
#ifdef CONFIG_SOC_MIMXRT1176_CM4
|
||||
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure BUS using SYS_PLL3_CLK */
|
||||
#ifdef CONFIG_SOC_MIMXRT1176_CM7
|
||||
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
|
||||
rootCfg.div = 2;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure BUS_LPSR using SYS_PLL3_CLK */
|
||||
#ifdef CONFIG_SOC_MIMXRT1176_CM4
|
||||
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
|
||||
rootCfg.div = 3;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure CSSYS using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
|
||||
|
||||
/* Configure CSTRACE using SYS_PLL2_CLK */
|
||||
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
|
||||
rootCfg.div = 4;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
|
||||
|
||||
/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
|
||||
#ifdef CONFIG_SOC_MIMXRT1176_CM4
|
||||
rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
|
||||
#ifdef CONFIG_SOC_MIMXRT1176_CM7
|
||||
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 240;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_MCUX_LPUART
|
||||
/* Configure Lpuart1 using SysPll2*/
|
||||
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
|
||||
rootCfg.div = 22;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
|
||||
|
||||
/* Configure Lpuart2 using SysPll2*/
|
||||
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
|
||||
rootCfg.div = 22;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_I2C_MCUX_LPI2C
|
||||
/* Configure Lpi2c1 using Osc48MDiv2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
|
||||
|
||||
/* Configure Lpi2c5 using Osc48MDiv2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPI_MCUX_LPSPI
|
||||
/* Configure lpspi using Osc48MDiv2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Keep core clock ungated during WFI */
|
||||
CCM->GPR_PRIVATE1_SET = 0x1;
|
||||
/* Keep the system clock running so SYSTICK can wake up the system from
|
||||
* wfi.
|
||||
*/
|
||||
GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_0, kGPC_RunMode);
|
||||
GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_1, kGPC_RunMode);
|
||||
GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_0, false);
|
||||
GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_1, false);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Perform basic hardware initialization
|
||||
*
|
||||
* Initialize the interrupt controller device drivers.
|
||||
* Also initialize the timer device driver, if required.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
|
||||
static int imxrt_init(const struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
unsigned int oldLevel; /* old interrupt lock level */
|
||||
|
||||
/* disable interrupts */
|
||||
oldLevel = irq_lock();
|
||||
|
||||
/* Disable Systick which might be enabled by bootrom */
|
||||
if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0) {
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#if CONFIG_SOC_MIMXRT1176_CM7
|
||||
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
|
||||
SCB_EnableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_MIMXRT1176_CM4
|
||||
/* Initialize Cache */
|
||||
/* Enable Code Bus Cache */
|
||||
if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) {
|
||||
/*
|
||||
* set command to invalidate all ways,
|
||||
* and write GO bit to initiate command
|
||||
*/
|
||||
LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK
|
||||
| LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_GO_MASK;
|
||||
/* Wait until the command completes */
|
||||
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
|
||||
}
|
||||
/* Enable cache, enable write buffer */
|
||||
LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK
|
||||
| LMEM_PCCCR_ENCACHE_MASK);
|
||||
}
|
||||
|
||||
/* Enable System Bus Cache */
|
||||
if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK)) {
|
||||
/*
|
||||
* set command to invalidate all ways,
|
||||
* and write GO bit to initiate command
|
||||
*/
|
||||
LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK
|
||||
| LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_GO_MASK;
|
||||
/* Wait until the command completes */
|
||||
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
|
||||
}
|
||||
/* Enable cache, enable write buffer */
|
||||
LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK
|
||||
| LMEM_PSCCR_ENCACHE_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Initialize system clock */
|
||||
clock_init();
|
||||
|
||||
/*
|
||||
* install default handler that simply resets the CPU
|
||||
* if configured in the kernel, NOP otherwise
|
||||
*/
|
||||
NMI_INIT();
|
||||
|
||||
/* restore interrupt state */
|
||||
irq_unlock(oldLevel);
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);
|
||||
Loading…
Add table
Add a link
Reference in a new issue