soc: arm: nxp_imx: add rt117x support

1. Added RT10xx and RT11xx configs
2. Added a new soc file for rt117x. There are clock differences
   between the RT10xx and RT11xx series, hence the soc files
   have been separated.

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>

soc/arm/common/cortex_m/arm_mpu_mem_cfg.h

@@ -56,6 +56,8 @@
 #define REGION_SRAM_SIZE REGION_4M
 #elif CONFIG_SRAM_SIZE == 32768
 #define REGION_SRAM_SIZE REGION_32M
+#elif CONFIG_SRAM_SIZE == 65536
+#define REGION_SRAM_SIZE REGION_64M
 #else
 #error "Unsupported sram size configuration"
 #endif

soc/arm/nxp_imx/rt/CMakeLists.txt

@@ -1,12 +1,10 @@
 #
-# Copyright (c) 2017, NXP
+# Copyright (c) 2017-2021, NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
-
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX soc_rt11xx.c)
-zephyr_sources(
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c)
-  soc.c
-  )
 
 zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER
   ROM_START SORT_KEY 0 boot_header.ld)

soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4

@@ -0,0 +1,17 @@
+# i.MX RT1170 CM4
+
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMXRT1176_CM4
+
+config SOC
+	default "mimxrt1176_cm4"
+
+config NUM_IRQS
+	default 218
+
+config GPIO
+	default y
+
+endif # SOC_MIMXRT1170_CM4

soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7

@@ -0,0 +1,17 @@
+# i.MX RT1170 CM7
+
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMXRT1176_CM7
+
+config SOC
+	default "mimxrt1176_cm7"
+
+config NUM_IRQS
+	default 218
+
+config GPIO
+	default y
+
+endif # SOC_MIMXRT1176_CM7

soc/arm/nxp_imx/rt/Kconfig.defconfig.series

@@ -1,6 +1,6 @@
 # i.MX RT series
 
-# Copyright (c) 2017, NXP
+# Copyright (c) 2017-2021, NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_IMX_RT
@@ -20,6 +20,10 @@ config CLOCK_CONTROL_MCUX_CCM
 	default y if HAS_MCUX_CCM
 	depends on CLOCK_CONTROL
 
+config CLOCK_CONTROL_MCUX_CCM_REV2
+	default y if HAS_MCUX_CCM_REV2
+	depends on CLOCK_CONTROL
+
 config DISPLAY_MCUX_ELCDIF
 	default y if HAS_MCUX_ELCDIF
 	depends on DISPLAY
@@ -76,30 +80,47 @@ endif # CODE_SEMC
 if CODE_ITCM
 
 config FLASH_SIZE
-	default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K)
+	default $(dt_node_reg_size_int,/soc/flexram@40028000/itcm@0,0,K) if SOC_SERIES_IMX_RT11XX
+	default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K) if SOC_SERIES_IMX_RT10XX
 
 config FLASH_BASE_ADDRESS
-	default $(dt_node_reg_addr_hex,/soc/flexram@400b0000/itcm@0)
+	default $(dt_node_reg_addr_hex,/soc/flexram@40028000/itcm@0) if SOC_SERIES_IMX_RT11XX
+	default $(dt_node_reg_addr_hex,/soc/flexram@400b0000/itcm@0) if SOC_SERIES_IMX_RT10XX
 
 endif # CODE_ITCM
 
+if CODE_SRAM0
+
+config FLASH_SIZE
+	default $(dt_node_reg_size_int,/soc/memory@1ffe0000,0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_node_reg_addr_hex,/soc/memory@1ffe0000)
+
+endif # CODE_SRAM0
+
+
 if CODE_FLEXSPI
 
 config FLASH_SIZE
-	default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K)
+	default $(dt_node_reg_size_int,/soc/spi@400cc000,1,K) if SOC_SERIES_IMX_RT11XX
+	default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K) if SOC_SERIES_IMX_RT10XX
 
 config FLASH_BASE_ADDRESS
-	default $(dt_node_reg_addr_hex,/soc/spi@402a8000,1)
+	default $(dt_node_reg_addr_hex,/soc/spi@400cc000,1) if SOC_SERIES_IMX_RT11XX
+	default $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) if SOC_SERIES_IMX_RT10XX
 
 endif # CODE_FLEXSPI
 
 if CODE_FLEXSPI2
 
 config FLASH_SIZE
-	default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K)
+	default $(dt_node_reg_size_int,/soc/spi@4000d000,1,K) if SOC_SERIES_IMX_RT11XX
+	default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K) if SOC_SERIES_IMX_RT10XX
 
 config FLASH_BASE_ADDRESS
-	default $(dt_node_reg_addr_hex,/soc/spi@402a4000,1)
+	default $(dt_node_reg_addr_hex,/soc/spi@4000d000,1) if SOC_SERIES_IMX_RT11XX
+	default $(dt_node_reg_addr_hex,/soc/spi@402a4000,1) if SOC_SERIES_IMX_RT10XX
 
 endif # CODE_FLEXSPI2
 

soc/arm/nxp_imx/rt/Kconfig.series

@@ -1,13 +1,11 @@
 # iMX RT series
 
-# Copyright (c) 2017, NXP
+# Copyright (c) 2017-2021, NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_IMX_RT
 	bool "i.MX RT Series"
 	select ARM
-	select CPU_CORTEX_M7
-	select CPU_CORTEX_M_HAS_DWT
 	select SOC_FAMILY_IMX
 	select CLOCK_CONTROL
 	help

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -1,6 +1,6 @@
 # i.MX RT series
 
-# Copyright (c) 2017-2020, NXP
+# Copyright (c) 2017-2021, NXP
 # SPDX-License-Identifier: Apache-2.0
 
 choice
@@ -9,6 +9,7 @@ choice
 
 config SOC_MIMXRT1011
 	bool "SOC_MIMXRT1011"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -30,6 +31,7 @@ config SOC_MIMXRT1011
 
 config SOC_MIMXRT1015
 	bool "SOC_MIMXRT1015"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -52,6 +54,7 @@ config SOC_MIMXRT1015
 
 config SOC_MIMXRT1021
 	bool "SOC_MIMXRT1021"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -77,6 +80,7 @@ config SOC_MIMXRT1021
 
 config SOC_MIMXRT1024
 	bool "SOC_MIMXRT1024"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -101,6 +105,7 @@ config SOC_MIMXRT1024
 
 config SOC_MIMXRT1051
 	bool "SOC_MIMXRT1051"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -127,6 +132,7 @@ config SOC_MIMXRT1051
 
 config SOC_MIMXRT1052
 	bool "SOC_MIMXRT1052"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -157,6 +163,7 @@ config SOC_MIMXRT1052
 
 config SOC_MIMXRT1061
 	bool "SOC_MIMXRT1061"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -183,6 +190,7 @@ config SOC_MIMXRT1061
 
 config SOC_MIMXRT1062
 	bool "SOC_MIMXRT1062"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -213,6 +221,7 @@ config SOC_MIMXRT1062
 
 config SOC_MIMXRT1064
 	bool "SOC_MIMXRT1064"
+	select SOC_SERIES_IMX_RT10XX
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
@@ -241,6 +250,48 @@ config SOC_MIMXRT1064
 	select HAS_MCUX_EDMA
 	select HAS_MCUX_FLEXCAN
 
+config SOC_MIMXRT1176_CM7
+	bool "SOC_MIMXRT1176_CM7"
+	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_DWT
+	select SOC_SERIES_IMX_RT11XX
+	select HAS_MCUX_CACHE
+	select HAS_MCUX
+	select HAS_MCUX_SEMC
+	select HAS_MCUX_CCM_REV2
+	select HAS_MCUX_IGPIO
+	select HAS_MCUX_LPI2C
+	select HAS_MCUX_LPSPI
+	select HAS_MCUX_LPUART
+	select CPU_HAS_ARM_MPU
+	select INIT_ARM_PLL
+	select INIT_ENET_PLL if NET_L2_ETHERNET
+	select INIT_VIDEO_PLL
+	select HAS_MCUX_EDMA
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select ADJUST_DCDC
+	select BYPASS_LDO_LPSR
+	select ADJUST_LDO
+
+config SOC_MIMXRT1176_CM4
+	bool "SOC_MIMXRT1176_CM4"
+	select CPU_CORTEX_M4
+	select SOC_SERIES_IMX_RT11XX
+	select HAS_MCUX_CACHE
+	select HAS_MCUX
+	select HAS_MCUX_SEMC
+	select HAS_MCUX_CCM_REV2
+	select HAS_MCUX_IGPIO
+	select HAS_MCUX_LPI2C
+	select HAS_MCUX_LPSPI
+	select HAS_MCUX_LPUART
+	select HAS_MCUX_GPT
+	select CPU_HAS_ARM_MPU
+	select INIT_ARM_PLL
+	select INIT_ENET_PLL if NET_L2_ETHERNET
+	select INIT_VIDEO_PLL
+	select HAS_MCUX_EDMA
+
 endchoice
 
 if SOC_SERIES_IMX_RT
@@ -317,6 +368,45 @@ config SOC_PART_NUMBER_MIMXRT1064CVL5A
 config SOC_PART_NUMBER_MIMXRT1064DVL6A
 	bool
 
+config SOC_PART_NUMBER_MIMXRT1176AVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1176CVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1176DVMAA
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1175AVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1175CVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1175DVMAA
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1173CVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1172AVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1172CVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1172DVMAA
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1171AVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1171CVM8A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1171DVMAA
+	bool
+
 config SOC_PART_NUMBER_IMX_RT
 	string
 	default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A
@@ -343,11 +433,32 @@ config SOC_PART_NUMBER_IMX_RT
 	default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
 	default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
 	default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A
+	default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A
+	default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A
+	default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA
+	default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A
+	default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A
+	default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA
+	default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A
+	default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A
+	default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A
+	default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA
+	default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A
+	default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A
+	default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA
 	help
 	  This string holds the full part number of the SoC. It is a hidden option
 	  that you should not set directly. The part number selection choice defines
 	  the default value for this string.
 
+config SOC_SERIES_IMX_RT10XX
+	bool "i.MX RT 10XX Series"
+	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_DWT
+
+config SOC_SERIES_IMX_RT11XX
+	bool "i.MX RT 11XX Series"
+
 config INIT_ARM_PLL
 	bool "Initialize ARM PLL"
 
@@ -374,14 +485,26 @@ config HAS_ARM_DIV
 config ARM_DIV
 	int "ARM clock divider"
 	range 0 7
+	default 0
 
 config AHB_DIV
 	int "AHB clock divider"
 	range 0 7
+	default 0
 
 config IPG_DIV
 	int "IPG clock divider"
 	range 0 3
+	default 0
+
+config ADJUST_DCDC
+	bool "Adjust internal DCDC output"
+
+config BYPASS_LDO_LPSR
+	bool "Bypass LDO lpsr"
+
+config ADJUST_LDO
+	bool "Adjust LDO setting"
 
 menuconfig NXP_IMX_RT_BOOT_HEADER
 	bool "Enable the boot header"
@@ -417,7 +540,7 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET
 	  FlexSPI configuration block consists of parameters regarding specific
 	  flash devices including read command sequence, quad mode enablement
 	  sequence (optional), etc. The boot ROM expectes FlexSPI configuration
-	  parameter to be presented in serail nor flash.
+	  parameter to be presented in serial nor flash.
 
 config IMAGE_VECTOR_TABLE_OFFSET
 	hex "Image vector table offset"
@@ -455,6 +578,8 @@ config CODE_FLEXSPI2
 	bool "Link code into internal FlexSPI-controlled memory"
 	select NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
 
+config CODE_SRAM0
+	bool "Link code into RAM_L memory (RAM_L)"
 endchoice
 
 endif # SOC_SERIES_IMX_RT

soc/arm/nxp_imx/rt/soc_rt11xx.c

@@ -0,0 +1,430 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <linker/sections.h>
+#include <linker/linker-defs.h>
+#include <fsl_clock.h>
+#include <fsl_gpc.h>
+#include <fsl_pmu.h>
+#include <fsl_dcdc.h>
+#include <arch/cpu.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#include <fsl_flexspi_nor_boot.h>
+#if CONFIG_USB_DC_NXP_EHCI
+#include "usb_phy.h"
+#include "usb_dc_mcux.h"
+#endif
+
+#if CONFIG_USB_DC_NXP_EHCI /* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL (0x0CU)
+#define BOARD_USB_PHY_TXCAL45DP (0x06U)
+#define BOARD_USB_PHY_TXCAL45DM (0x06U)
+#endif
+
+#ifdef CONFIG_INIT_ARM_PLL
+static const clock_arm_pll_config_t armPllConfig = {
+	/* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+	.postDivider = kCLOCK_PllPostDiv2,
+	/* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+	.loopDivider = 166,
+};
+#endif
+
+static const clock_sys_pll2_config_t sysPll2Config = {
+	/* Denominator of spread spectrum */
+	.mfd = 268435455,
+	/* Spread spectrum parameter */
+	.ss = NULL,
+	/* Enable spread spectrum or not */
+	.ssEnable = false,
+};
+
+#ifdef CONFIG_INIT_ENET_PLL
+static const clock_sys_pll1_config_t sysPll1Config = {
+	.pllDiv2En = true,
+};
+#endif
+
+#ifdef CONFIG_INIT_VIDEO_PLL
+static const clock_video_pll_config_t videoPllConfig = {
+	/* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
+	.loopDivider = 41,
+	/* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
+	.postDivider = 0,
+	/*
+	 * 30 bit numerator of fractional loop divider,
+	 * Fout = Fin * ( loopDivider + numerator / denominator )
+	 */
+	.numerator = 1,
+	/*
+	 * 30 bit denominator of fractional loop divider,
+	 * Fout = Fin * ( loopDivider + numerator / denominator )
+	 */
+	.denominator = 960000,
+	/* Spread spectrum parameter */
+	.ss = NULL,
+	/* Enable spread spectrum or not */
+	.ssEnable = false,
+};
+#endif
+
+#if CONFIG_USB_DC_NXP_EHCI
+	usb_phy_config_struct_t usbPhyConfig = {
+		BOARD_USB_PHY_D_CAL,
+		BOARD_USB_PHY_TXCAL45DP,
+		BOARD_USB_PHY_TXCAL45DM,
+	};
+#endif
+
+#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
+const __imx_boot_data_section BOOT_DATA_T boot_data = {
+	.start = CONFIG_FLASH_BASE_ADDRESS,
+	.size = KB(CONFIG_FLASH_SIZE),
+	.plugin = PLUGIN_FLAG,
+	.placeholder = 0xFFFFFFFF,
+};
+
+extern char __start[];
+const __imx_boot_ivt_section ivt image_vector_table = {
+	.hdr = IVT_HEADER,
+	.entry = (uint32_t) __start,
+	.reserved1 = IVT_RSVD,
+#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
+	.dcd = (uint32_t) dcd_data,
+#else
+	.dcd = (uint32_t) NULL,
+#endif
+	.boot_data = (uint32_t) &boot_data,
+	.self = (uint32_t) &image_vector_table,
+	.csf = (uint32_t)CSF_ADDRESS,
+	.reserved2 = IVT_RSVD,
+};
+#endif
+
+/**
+ *
+ * @brief Initialize the system clock
+ *
+ * @return N/A
+ *
+ */
+static ALWAYS_INLINE void clock_init(void)
+{
+	clock_root_config_t rootCfg = {0};
+
+#if CONFIG_ADJUST_DCDC
+	DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
+#endif
+
+	/* Check if FBB need to be enabled in OverDrive(OD) mode */
+	if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) {
+		PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
+	} else {
+		PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
+	}
+
+#if CONFIG_BYPASS_LDO_LPSR
+	PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
+	PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
+#endif
+
+#if CONFIG_ADJUST_LDO
+	pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
+	pmu_static_lpsr_dig_config_t lpsrDigConfig;
+
+	if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &
+		ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) {
+		PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
+		PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
+	}
+
+	if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &
+		ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) {
+		PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
+		lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
+		PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
+	}
+#endif
+
+	/* PLL LDO shall be enabled first before enable PLLs */
+
+	/* Config CLK_1M */
+	CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+	/* Init OSC RC 16M */
+	ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
+
+	/* Init OSC RC 400M */
+	CLOCK_OSC_EnableOscRc400M();
+	CLOCK_OSC_GateOscRc400M(true);
+
+	/* Init OSC RC 48M */
+	CLOCK_OSC_EnableOsc48M(true);
+	CLOCK_OSC_EnableOsc48MDiv2(true);
+
+	/* Config OSC 24M */
+	ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) |
+				    ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) |
+				    ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) |
+				    ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) |
+				    ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+
+	/* Wait for 24M OSC to be stable. */
+	while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+		(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {
+	}
+
+	/* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
+	rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+
+#if CONFIG_SOC_MIMXRT1176_CM7
+	CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+	CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+#if CONFIG_SOC_MIMXRT1176_CM4
+	CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+	CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+#endif
+
+	/*
+	 * If DCD is used, please make sure the clock source of SEMC is not
+	 * changed in the following PLL/PFD configuration code.
+	 */
+
+#ifdef CONFIG_INIT_ARM_PLL
+	/* Init Arm Pll. */
+	CLOCK_InitArmPll(&armPllConfig);
+#endif
+
+#ifdef CONFIG_INIT_ENET_PLL
+	CLOCK_InitSysPll1(&sysPll1Config);
+#else
+	/* Bypass Sys Pll1. */
+	CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
+
+	/* DeInit Sys Pll1. */
+	CLOCK_DeinitSysPll1();
+#endif
+
+	/* Init Sys Pll2. */
+	CLOCK_InitSysPll2(&sysPll2Config);
+
+	/* Init System Pll2 pfd0. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+
+	/* Init System Pll2 pfd1. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+
+	/* Init System Pll2 pfd2. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+
+	/* Init System Pll2 pfd3. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+	/* Init Sys Pll3. */
+	CLOCK_InitSysPll3();
+
+	/* Init System Pll3 pfd0. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
+
+	/* Init System Pll3 pfd1. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
+
+	/* Init System Pll3 pfd2. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
+
+	/* Init System Pll3 pfd3. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
+
+#ifdef CONFIG_INIT_VIDEO_PLL
+	/* Init Video Pll. */
+	CLOCK_InitVideoPll(&videoPllConfig);
+#endif
+
+	/* Module clock root configurations. */
+	/* Configure M7 using ARM_PLL_CLK */
+#ifdef CONFIG_SOC_MIMXRT1176_CM7
+	rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+	/* Configure M4 using SYS_PLL3_PFD3_CLK */
+#ifdef CONFIG_SOC_MIMXRT1176_CM4
+	rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+#endif
+
+	/* Configure BUS using SYS_PLL3_CLK */
+#ifdef CONFIG_SOC_MIMXRT1176_CM7
+	rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
+#endif
+
+	/* Configure BUS_LPSR using SYS_PLL3_CLK */
+#ifdef CONFIG_SOC_MIMXRT1176_CM4
+	rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
+	rootCfg.div = 3;
+	CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+#endif
+
+	/* Configure CSSYS using OSC_RC_48M_DIV2 */
+	rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
+
+	/* Configure CSTRACE using SYS_PLL2_CLK */
+	rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
+	rootCfg.div = 4;
+	CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
+
+	/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
+#ifdef CONFIG_SOC_MIMXRT1176_CM4
+	rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
+#endif
+
+	/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
+#ifdef CONFIG_SOC_MIMXRT1176_CM7
+	rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 240;
+	CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+#ifdef CONFIG_UART_MCUX_LPUART
+	/* Configure Lpuart1 using SysPll2*/
+	rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
+	rootCfg.div = 22;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
+
+	/* Configure Lpuart2 using SysPll2*/
+	rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
+	rootCfg.div = 22;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
+#endif
+
+#ifdef CONFIG_I2C_MCUX_LPI2C
+	/* Configure Lpi2c1 using Osc48MDiv2 */
+	rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
+
+	/* Configure Lpi2c5 using Osc48MDiv2 */
+	rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
+#endif
+
+#ifdef CONFIG_SPI_MCUX_LPSPI
+	/* Configure lpspi using Osc48MDiv2 */
+	rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
+#endif
+
+	/* Keep core clock ungated during WFI */
+	CCM->GPR_PRIVATE1_SET = 0x1;
+	/* Keep the system clock running so SYSTICK can wake up the system from
+	 * wfi.
+	 */
+	GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_0, kGPC_RunMode);
+	GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_1, kGPC_RunMode);
+	GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_0, false);
+	GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_1, false);
+}
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * Initialize the interrupt controller device drivers.
+ * Also initialize the timer device driver, if required.
+ *
+ * @return 0
+ */
+
+static int imxrt_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	unsigned int oldLevel; /* old interrupt lock level */
+
+	/* disable interrupts */
+	oldLevel = irq_lock();
+
+	/* Disable Systick which might be enabled by bootrom */
+	if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0) {
+		SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	}
+
+#if CONFIG_SOC_MIMXRT1176_CM7
+	if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
+		SCB_EnableICache();
+	}
+	if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
+		SCB_EnableDCache();
+	}
+#endif
+
+#if CONFIG_SOC_MIMXRT1176_CM4
+	/* Initialize Cache */
+	/* Enable Code Bus Cache */
+	if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) {
+		/*
+		 * set command to invalidate all ways,
+		 * and write GO bit to initiate command
+		 */
+		LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK
+			| LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_GO_MASK;
+		/* Wait until the command completes */
+		while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
+		}
+		/* Enable cache, enable write buffer */
+		LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK
+				| LMEM_PCCCR_ENCACHE_MASK);
+	}
+
+	/* Enable System Bus Cache */
+	if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK)) {
+		/*
+		 * set command to invalidate all ways,
+		 * and write GO bit to initiate command
+		 */
+		LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK
+			| LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_GO_MASK;
+		/* Wait until the command completes */
+		while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
+		}
+		/* Enable cache, enable write buffer */
+		LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK
+				| LMEM_PSCCR_ENCACHE_MASK);
+	}
+#endif
+
+	/* Initialize system clock */
+	clock_init();
+
+	/*
+	 * install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	/* restore interrupt state */
+	irq_unlock(oldLevel);
+	return 0;
+}
+
+SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);