boards: mimxrt1020_evk: Added support for SPI on RT1020
Adds support for LPSPI1 on RT1020. This peripheral is exposed on J19, as pins 3, 4, 5, and 6 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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5 changed files with 52 additions and 4 deletions
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@ -77,6 +77,8 @@ features:
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| SDHC | on-chip | disk access |
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| SDHC | on-chip | disk access |
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@ -128,13 +130,13 @@ The MIMXRT1020 SoC has five pairs of pinmux/gpio controllers.
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet |
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| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_10 | ENET_RX_DATA00 | Ethernet |
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| GPIO_AD_B0_10 | ENET_RX_DATA00/LPSPI1_SCK | Ethernet/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_11 | ENET_RX_EN | Ethernet |
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| GPIO_AD_B0_11 | ENET_RX_EN/LPSPI1_PCS0 | Ethernet/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_12 | ENET_RX_ER | Ethernet |
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| GPIO_AD_B0_12 | ENET_RX_ER/LPSPI1_SDO | Ethernet/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_13 | ENET_TX_EN | Ethernet |
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| GPIO_AD_B0_13 | ENET_TX_EN/LPSPI1_SDI | Ethernet/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet |
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| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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@ -138,6 +138,10 @@ arduino_serial: &lpuart2 {};
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current-speed = <115200>;
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current-speed = <115200>;
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};
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};
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&lpspi1 {
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status = "okay";
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};
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&enet {
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&enet {
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status = "okay";
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status = "okay";
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ptp {
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ptp {
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@ -21,4 +21,5 @@ supported:
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- gpio
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- gpio
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- i2c
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- i2c
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- netif:eth
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- netif:eth
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- spi
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- usb_device
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- usb_device
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@ -223,6 +223,40 @@ static int mimxrt1020_evk_init(const struct device *dev)
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GPIO_WritePinOutput(GPIO1, 4, 0);
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GPIO_WritePinOutput(GPIO1, 4, 0);
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
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#error "LPSPI1 and ENET share pins on this board, please disable one" \
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"using KConfig or the devicetree"
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#else
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/* LPSPI1 CS, SDO, SDI, CLK exposed as pins 3, 4, 5, and 6 on J19 */
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/* GPIO_AD_B0_10 is configured as LPSPI1_SCK */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK, 0U);
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/* GPIO_AD_B0_11 is configured as LPSPI1_PCS0 */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0, 0U);
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/* GPIO_AD_B0_12 is configured as LPSPI1_SDO */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO, 0U);
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/* GPIO_AD_B0_13 is configured as LPSPI1_SDI */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
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mimxrt1020_evk_usdhc_pinmux(0, true, 2, 1);
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mimxrt1020_evk_usdhc_pinmux(0, true, 2, 1);
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imxrt_usdhc_pinmux_cb_register(mimxrt1020_evk_usdhc_pinmux);
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imxrt_usdhc_pinmux_cb_register(mimxrt1020_evk_usdhc_pinmux);
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2021, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_1"
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