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drivers: udc_dwc2: Add power saving related registers

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Add Power and clock gating control register to register map and
appropriate bit macros. Add missing GHWCFG4, GLPMCFG and GPWRDN bits.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This commit is contained in:
Tomasz Moń 2024-08-23 09:26:19 +02:00 • committed by Fabio Baltieri
commit 42f2e1c18b
1 changed files with 184 additions and 5 deletions
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189
drivers/usb/common/usb_dwc2_hw.h
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@ -110,13 +110,12 @@ struct usb_dwc2_reg {
volatile uint32_t reserved5[16];
struct usb_dwc2_in_ep in_ep[16];
struct usb_dwc2_out_ep out_ep[16];
volatile uint32_t reserved6[64];
volatile uint32_t pcgcctl;
};
/*
* With the maximum number of supported endpoints, register map
* of the controller must be equal to 0x0D00.
*/
BUILD_ASSERT(sizeof(struct usb_dwc2_reg) == 0x0D00);
/* The last register (PCGCCTL) must be at offset 0xE00. */
BUILD_ASSERT(offsetof(struct usb_dwc2_reg, pcgcctl) == 0x0E00);
/*
* GET_FIELD/SET_FIELD macros below are intended to be used to define functions
@ -430,14 +429,46 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_xfersizewidth, GHWCFG3_XFERSIZEWIDTH)
/* GHWCFG4 register */
#define USB_DWC2_GHWCFG4 0x0050UL
#define USB_DWC2_GHWCFG4_DESCDMA_POS 31UL
#define USB_DWC2_GHWCFG4_DESCDMA BIT(USB_DWC2_GHWCFG4_DESCDMA_POS)
#define USB_DWC2_GHWCFG4_DESCDMAENABLED_POS 30UL
#define USB_DWC2_GHWCFG4_DESCDMAENABLED BIT(USB_DWC2_GHWCFG4_DESCDMAENABLED_POS)
#define USB_DWC2_GHWCFG4_INEPS_POS 26UL
#define USB_DWC2_GHWCFG4_INEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_INEPS_POS)
#define USB_DWC2_GHWCFG4_DEDFIFOMODE_POS 25UL
#define USB_DWC2_GHWCFG4_DEDFIFOMODE BIT(USB_DWC2_GHWCFG4_DEDFIFOMODE_POS)
#define USB_DWC2_GHWCFG4_SESSENDFLTR_POS 24UL
#define USB_DWC2_GHWCFG4_SESSENDFLTR BIT(USB_DWC2_GHWCFG4_SESSENDFLTR_POS)
#define USB_DWC2_GHWCFG4_BVALIDFLTR_POS 23UL
#define USB_DWC2_GHWCFG4_BVALIDFLTR BIT(USB_DWC2_GHWCFG4_BVALIDFLTR_POS)
#define USB_DWC2_GHWCFG4_AVALIDFLTR_POS 22UL
#define USB_DWC2_GHWCFG4_AVALIDFLTR BIT(USB_DWC2_GHWCFG4_AVALIDFLTR_POS)
#define USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS 21UL
#define USB_DWC2_GHWCFG4_VBUSVALIDFLTR BIT(USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS)
#define USB_DWC2_GHWCFG4_IDDGFLTR_POS 20UL
#define USB_DWC2_GHWCFG4_IDDGFLTR BIT(USB_DWC2_GHWCFG4_IDDGFLTR_POS)
#define USB_DWC2_GHWCFG4_NUMCTLEPS_POS 16UL
#define USB_DWC2_GHWCFG4_NUMCTLEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMCTLEPS_POS)
#define USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS 14UL
#define USB_DWC2_GHWCFG4_PHYDATAWIDTH_MASK (0x3UL << USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS)
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS 13UL
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS)
#define USB_DWC2_GHWCFG4_ACGSUPT_POS 12UL
#define USB_DWC2_GHWCFG4_ACGSUPT BIT(USB_DWC2_GHWCFG4_ACGSUPT_POS)
#define USB_DWC2_GHWCFG4_IPGISOCSUPT_POS 11UL
#define USB_DWC2_GHWCFG4_IPGISOCSUPT BIT(USB_DWC2_GHWCFG4_IPGISOCSUPT_POS)
#define USB_DWC2_GHWCFG4_SERVINTFLOW_POS 10UL
#define USB_DWC2_GHWCFG4_SERVINTFLOW BIT(USB_DWC2_GHWCFG4_SERVINTFLOW_POS)
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS 9UL
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1 BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS)
#define USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS 7UL
#define USB_DWC2_GHWCFG4_EXT_HIBERNATION BIT(USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS)
#define USB_DWC2_GHWCFG4_HIBERNATION_POS 6UL
#define USB_DWC2_GHWCFG4_HIBERNATION BIT(USB_DWC2_GHWCFG4_HIBERNATION_POS)
#define USB_DWC2_GHWCFG4_AHBFREQ_POS 5UL
#define USB_DWC2_GHWCFG4_AHBFREQ BIT(USB_DWC2_GHWCFG4_AHBFREQ_POS)
#define USB_DWC2_GHWCFG4_PARTIALPWRDN_POS 4UL
#define USB_DWC2_GHWCFG4_PARTIALPWRDN BIT(USB_DWC2_GHWCFG4_PARTIALPWRDN_POS)
#define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS 0UL
#define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS)
@ -446,6 +477,130 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numctleps, GHWCFG4_NUMCTLEPS)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_phydatawidth, GHWCFG4_PHYDATAWIDTH)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numdevperioeps, GHWCFG4_NUMDEVPERIOEPS)
/* LPM Config Register */
#define USB_DWC2_GLPMCFG 0x0054UL
#define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS 29UL
#define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS BIT(USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS)
#define USB_DWC2_GLPMCFG_LPM_ENBESL_POS 28UL
#define USB_DWC2_GLPMCFG_LPM_ENBESL BIT(USB_DWC2_GLPMCFG_LPM_ENBESL_POS)
#define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS 25UL
#define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS)
#define USB_DWC2_GLPMCFG_SNDLPM_POS 24UL
#define USB_DWC2_GLPMCFG_SNDLPM BIT(USB_DWC2_GLPMCFG_SNDLPM_POS)
/* Host mode LPM Retry Count and LPM Channel Index */
#define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS 21UL
#define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS)
#define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS 17UL
#define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_MASK (0xFUL << USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS)
/* Device mode LPM Accept Control */
#define USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS 23UL
#define USB_DWC2_GLPMCFG_LPM_ACK_BULK BIT(USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS)
#define USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS 22UL
#define USB_DWC2_GLPMCFG_LPM_ACK_ISO BIT(USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS)
#define USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS 21UL
#define USB_DWC2_GLPMCFG_LPM_NYET_CTRL BIT(USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS)
#define USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS 20UL
#define USB_DWC2_GLPMCFG_LPM_ACK_INTR BIT(USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS)
#define USB_DWC2_GLPMCFG_L1RESUMEOK_POS 16UL
#define USB_DWC2_GLPMCFG_L1RESUMEOK BIT(USB_DWC2_GLPMCFG_L1RESUMEOK_POS)
#define USB_DWC2_GLPMCFG_SLPSTS_POS 15UL
#define USB_DWC2_GLPMCFG_SLPSTS BIT(USB_DWC2_GLPMCFG_SLPSTS_POS)
#define USB_DWC2_GLPMCFG_COREL1RES_POS 13UL
#define USB_DWC2_GLPMCFG_COREL1RES_MASK (0x3UL << USB_DWC2_GLPMCFG_COREL1RES_POS)
#define USB_DWC2_GLPMCFG_COREL1RES_ERROR 0
#define USB_DWC2_GLPMCFG_COREL1RES_STALL 1
#define USB_DWC2_GLPMCFG_COREL1RES_NYET 2
#define USB_DWC2_GLPMCFG_COREL1RES_ACK 3
#define USB_DWC2_GLPMCFG_HIRD_THRES_POS 8UL
#define USB_DWC2_GLPMCFG_HIRD_THRES_MASK (0x1FUL << USB_DWC2_GLPMCFG_HIRD_THRES_POS)
#define USB_DWC2_GLPMCFG_ENBLSLPM_POS 7UL
#define USB_DWC2_GLPMCFG_ENBLSLPM BIT(USB_DWC2_GLPMCFG_ENBLSLPM_POS)
#define USB_DWC2_GLPMCFG_BREMOTEWAKE_POS 6UL
#define USB_DWC2_GLPMCFG_BREMOTEWAKE BIT(USB_DWC2_GLPMCFG_BREMOTEWAKE_POS)
#define USB_DWC2_GLPMCFG_HIRD_POS 2UL
#define USB_DWC2_GLPMCFG_HIRD_MASK (0xFUL << USB_DWC2_GLPMCFG_HIRD_POS)
#define USB_DWC2_GLPMCFG_APPL1RES_POS 1UL
#define USB_DWC2_GLPMCFG_APPL1RES BIT(USB_DWC2_GLPMCFG_APPL1RES_POS)
#define USB_DWC2_GLPMCFG_LPMCAP_POS 0UL
#define USB_DWC2_GLPMCFG_LPMCAP BIT(USB_DWC2_GLPMCFG_LPMCAP_POS)
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retrycnt_sts, GLPMCFG_LPM_RETRYCNT_STS)
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT)
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX)
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_corel1res, GLPMCFG_COREL1RES)
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES)
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD)
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT)
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX)
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES)
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD)
/* Global Power Down Register */
#define USB_DWC2_GPWRDN 0x0058UL
#define USB_DWC2_GPWRDN_MULTVALIDBC_POS 24UL
#define USB_DWC2_GPWRDN_MULTVALIDBC_MASK (0x1FUL << USB_DWC2_GPWRDN_MULTVALIDBC_POS)
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_0 0
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C 1
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B 2
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A 4
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_GND 8
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A_GND 12
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_FLOAT 16
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C_FLOAT 17
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B_FLOAT 18
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_1 31
#define USB_DWC2_GPWRDN_BSESSVLD_POS 22UL
#define USB_DWC2_GPWRDN_BSESSVLD BIT(USB_DWC2_GPWRDN_BSESSVLD_POS)
#define USB_DWC2_GPWRDN_IDDIG_POS 21UL
#define USB_DWC2_GPWRDN_IDDIG BIT(USB_DWC2_GPWRDN_IDDIG_POS)
#define USB_DWC2_GPWRDN_LINESTATE_POS 19UL
#define USB_DWC2_GPWRDN_LINESTATE_MASK (0x3UL << USB_DWC2_GPWRDN_LINESTATE_POS)
#define USB_DWC2_GPWRDN_LINESTATE_DM0DP0 0
#define USB_DWC2_GPWRDN_LINESTATE_DM0DP1 1
#define USB_DWC2_GPWRDN_LINESTATE_DM1DP0 2
#define USB_DWC2_GPWRDN_LINESTATE_NOT_DEFINED 3
#define USB_DWC2_GPWRDN_STSCHNGINTMSK_POS 18UL
#define USB_DWC2_GPWRDN_STSCHNGINTMSK BIT(USB_DWC2_GPWRDN_STSCHNGINTMSK_POS)
#define USB_DWC2_GPWRDN_STSCHNGINT_POS 17UL
#define USB_DWC2_GPWRDN_STSCHNGINT BIT(USB_DWC2_GPWRDN_STSCHNGINT_POS)
#define USB_DWC2_GPWRDN_SRPDETECTMSK_POS 16UL
#define USB_DWC2_GPWRDN_SRPDETECTMSK BIT(USB_DWC2_GPWRDN_SRPDETECTMSK_POS)
#define USB_DWC2_GPWRDN_SRPDETECT_POS 15UL
#define USB_DWC2_GPWRDN_SRPDETECT BIT(USB_DWC2_GPWRDN_SRPDETECT_POS)
#define USB_DWC2_GPWRDN_CONNDETMSK_POS 14UL
#define USB_DWC2_GPWRDN_CONNDETMSK BIT(USB_DWC2_GPWRDN_CONNDETMSK_POS)
#define USB_DWC2_GPWRDN_CONNECTDET_POS 13UL
#define USB_DWC2_GPWRDN_CONNECTDET BIT(USB_DWC2_GPWRDN_CONNECTDET_POS)
#define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS 12UL
#define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK BIT(USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS)
#define USB_DWC2_GPWRDN_DISCONNECTDETECT_POS 11UL
#define USB_DWC2_GPWRDN_DISCONNECTDETECT BIT(USB_DWC2_GPWRDN_DISCONNECTDETECT_POS)
#define USB_DWC2_GPWRDN_RESETDETMSK_POS 10UL
#define USB_DWC2_GPWRDN_RESETDETMSK BIT(USB_DWC2_GPWRDN_RESETDETMSK_POS)
#define USB_DWC2_GPWRDN_RESETDETECTED_POS 9UL
#define USB_DWC2_GPWRDN_RESETDETECTED BIT(USB_DWC2_GPWRDN_RESETDETECTED_POS)
#define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS 8UL
#define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK BIT(USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS)
#define USB_DWC2_GPWRDN_LNSTSCHNG_POS 7UL
#define USB_DWC2_GPWRDN_LNSTSCHNG BIT(USB_DWC2_GPWRDN_LNSTSCHNG_POS)
#define USB_DWC2_GPWRDN_DISABLEVBUS_POS 6UL
#define USB_DWC2_GPWRDN_DISABLEVBUS BIT(USB_DWC2_GPWRDN_DISABLEVBUS_POS)
#define USB_DWC2_GPWRDN_PWRDNSWTCH_POS 5UL
#define USB_DWC2_GPWRDN_PWRDNSWTCH BIT(USB_DWC2_GPWRDN_PWRDNSWTCH_POS)
#define USB_DWC2_GPWRDN_PWRDNRST_N_POS 4UL
#define USB_DWC2_GPWRDN_PWRDNRST_N BIT(USB_DWC2_GPWRDN_PWRDNRST_N_POS)
#define USB_DWC2_GPWRDN_PWRDNCLMP_POS 3UL
#define USB_DWC2_GPWRDN_PWRDNCLMP BIT(USB_DWC2_GPWRDN_PWRDNCLMP_POS)
#define USB_DWC2_GPWRDN_RESTORE_POS 2UL
#define USB_DWC2_GPWRDN_RESTORE BIT(USB_DWC2_GPWRDN_RESTORE_POS)
#define USB_DWC2_GPWRDN_PMUACTV_POS 1UL
#define USB_DWC2_GPWRDN_PMUACTV BIT(USB_DWC2_GPWRDN_PMUACTV_POS)
#define USB_DWC2_GPWRDN_PMUINTSEL_POS 0UL
#define USB_DWC2_GPWRDN_PMUINTSEL BIT(USB_DWC2_GPWRDN_PMUINTSEL_POS)
USB_DWC2_GET_FIELD_DEFINE(gpwrdn_multvalidbc, GPWRDN_MULTVALIDBC)
USB_DWC2_GET_FIELD_DEFINE(gpwrdn_linestate, GPWRDN_LINESTATE)
/* GDFIFOCFG register */
#define USB_DWC2_GDFIFOCFG 0x005CUL
#define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS 16UL
@ -805,6 +960,30 @@ USB_DWC2_GET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
USB_DWC2_SET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT)
USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
/* Power and Clock Gating Control Register */
#define USB_DWC2_PCGCCTL 0x0E00UL
#define USB_DWC2_PCGCCTL_RESTOREVALUE_POS 14UL
#define USB_DWC2_PCGCCTL_RESTOREVALUE_MASK (0x3FFFFUL << USB_DWC2_PCGCCTL_RESTOREVALUE_POS)
#define USB_DWC2_PCGCCTL_ESSREGRESTORED_POS 13UL
#define USB_DWC2_PCGCCTL_ESSREGRESTORED BIT(USB_DWC2_PCGCCTL_ESSREGRESTORED_POS)
#define USB_DWC2_PCGCCTL_RESTOREMODE_POS 9UL
#define USB_DWC2_PCGCCTL_RESTOREMODE BIT(USB_DWC2_PCGCCTL_RESTOREMODE_POS)
#define USB_DWC2_PCGCCTL_L1SUSPENDED_POS 7UL
#define USB_DWC2_PCGCCTL_L1SUSPENDED BIT(USB_DWC2_PCGCCTL_L1SUSPENDED_POS)
#define USB_DWC2_PCGCCTL_PHYSLEEP_POS 6UL
#define USB_DWC2_PCGCCTL_PHYSLEEP BIT(USB_DWC2_PCGCCTL_PHYSLEEP_POS)
#define USB_DWC2_PCGCCTL_ENBL_L1GATING_POS 5UL
#define USB_DWC2_PCGCCTL_ENBL_L1GATING BIT(USB_DWC2_PCGCCTL_ENBL_L1GATING_POS)
#define USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS 3UL
#define USB_DWC2_PCGCCTL_RSTPDWNMODULE BIT(USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS)
#define USB_DWC2_PCGCCTL_GATEHCLK_POS 1UL
#define USB_DWC2_PCGCCTL_GATEHCLK BIT(USB_DWC2_PCGCCTL_GATEHCLK_POS)
#define USB_DWC2_PCGCCTL_STOPPCLK_POS 0UL
#define USB_DWC2_PCGCCTL_STOPPCLK BIT(USB_DWC2_PCGCCTL_STOPPCLK_POS)
USB_DWC2_GET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE)
USB_DWC2_SET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE)
/*
* Device IN/OUT endpoint transfer size register
* IN at offsets 0x0910 + (0x20 * n), n = 0 .. x,