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driver: clock: esp32: retrieve HW clock from DTS

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ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves 2022-12-21 10:46:18 -03:00 • committed by Anas Nashif
commit 42b33382f7
16 changed files with 23 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

2
boards/xtensa/esp32/esp32_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/esp32_net/esp32_net_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32_NET=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=n
CONFIG_SERIAL=n
CONFIG_UART_CONSOLE=n

2
boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig
View file

@ -6,8 +6,6 @@ CONFIG_BOARD_ESP32S2_FRANZININHO=y
CONFIG_SOC_ESP32S2=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
View file

@ -6,8 +6,6 @@ CONFIG_BOARD_ESP32S2_SAOLA=y
CONFIG_SOC_ESP32S2=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/odroid_go/odroid_go_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

2
boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig
View file

@ -7,8 +7,6 @@ CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

4
drivers/clock_control/clock_control_esp32.c
View file

@ -476,7 +476,7 @@ static const struct clock_control_driver_api clock_control_esp32_api = {
static const struct esp32_clock_config esp32_clock_config0 = {
.clk_src_sel = ESP32_CLOCK_SOURCE,
.cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
.cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / 10000000,
.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
.xtal_div = ESP32_CLOCK_XTAL_DIV
};
@ -492,6 +492,6 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
#ifndef CONFIG_SOC_ESP32C3
BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
MHZ(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency)),
DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
#endif

10
include/zephyr/dt-bindings/clock/esp32_clock.h
View file

@ -15,11 +15,11 @@
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
#define ESP32_CLK_CPU_26M 26U
#define ESP32_CLK_CPU_40M 40U
#define ESP32_CLK_CPU_80M 80U
#define ESP32_CLK_CPU_160M 160U
#define ESP32_CLK_CPU_240M 240U
#define ESP32_CLK_CPU_26M 26000000
#define ESP32_CLK_CPU_40M 40000000
#define ESP32_CLK_CPU_80M 80000000
#define ESP32_CLK_CPU_160M 160000000
#define ESP32_CLK_CPU_240M 240000000
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_24M 0U

4
include/zephyr/dt-bindings/clock/esp32c3_clock.h
View file

@ -14,8 +14,8 @@
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
#define ESP32_CLK_CPU_80M 80U
#define ESP32_CLK_CPU_160M 160U
#define ESP32_CLK_CPU_80M 80000000
#define ESP32_CLK_CPU_160M 160000000
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_32M 0U

10
include/zephyr/dt-bindings/clock/esp32s2_clock.h
View file

@ -14,11 +14,11 @@
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
#define ESP32_CLK_CPU_26M 26U
#define ESP32_CLK_CPU_40M 40U
#define ESP32_CLK_CPU_80M 80U
#define ESP32_CLK_CPU_160M 160U
#define ESP32_CLK_CPU_240M 240U
#define ESP32_CLK_CPU_26M 26000000
#define ESP32_CLK_CPU_40M 40000000
#define ESP32_CLK_CPU_80M 80000000
#define ESP32_CLK_CPU_160M 160000000
#define ESP32_CLK_CPU_240M 240000000
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_40M 0U

3
soc/xtensa/esp32/Kconfig.defconfig
View file

@ -45,6 +45,9 @@ endif
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC

3
soc/xtensa/esp32_net/Kconfig.defconfig
View file

@ -13,6 +13,9 @@ config SOC_TOOLCHAIN_NAME
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC

3
soc/xtensa/esp32s2/Kconfig.defconfig
View file

@ -46,6 +46,9 @@ config MP_MAX_NUM_CPUS
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC