driver: clock: npcx: Add valid clock checking
NPCX clock has some limitations about the frequency range & synchronization between core clock & other clocks. Add build assert to check whether NPCX clock setting correct. This also fixed soc_clock.h to consist with datasheet. Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This commit is contained in:
Wealian Liao
Anas Nashif
parent
8d48b919c6
commit
42aeaccb3e
3 changed files with 73 additions and 24 deletions
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@ -15,7 +15,7 @@ config CLOCK_NPCX_OSC_CYCLES_PER_SEC
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range 10000000 100000000
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depends on SOC_FAMILY_NPCX
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help
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Core Domain Clock Generator PLL frequency,
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Core Domain Clock (OSC_CLK) Generator PLL frequency,
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allowed values: From 10Mhz to 100Mhz.
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config CLOCK_NPCX_APB1_PRESCALER
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@ -24,15 +24,33 @@ config CLOCK_NPCX_APB1_PRESCALER
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range 1 10
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depends on SOC_FAMILY_NPCX
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help
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APB1 prescaler, allowed values: From 1 to 10.
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This sets the APB1 prescaler which changes the frequency of APB1_CLK.
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APB1_CLK frequency = OSC_CLK / APB1_PRE. The APB1 prescaler allowed
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value is from 1 to 10.
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The generated frequency of APB1_CLK should comply with the following
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requirements:
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- The frequency of APB1_CLK must be set to:
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4MHz <= APB1_CLK <= 50MHz.
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- The frequency of APB1_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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config CLOCK_NPCX_APB2_PRESCALER
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int "APB1 prescaler"
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int "APB2 prescaler"
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default 8
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range 1 10
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depends on SOC_FAMILY_NPCX
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help
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APB2 prescaler, allowed values: From 1 to 10.
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This sets the APB2 prescaler which changes the frequency of APB2_CLK.
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APB2_CLK frequency = OSC_CLK / APB2_PRE. The APB2 prescaler allowed
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value is from 1 to 10.
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The generated frequency of APB2_CLK should comply with the following
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requirements:
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- The frequency of APB2_CLK must be set to:
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8MHz <= APB2_CLK <= 50MHz.
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- The frequency of APB2_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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config CLOCK_NPCX_APB3_PRESCALER
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int "APB3 prescaler"
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@ -40,4 +58,13 @@ config CLOCK_NPCX_APB3_PRESCALER
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range 1 10
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depends on SOC_FAMILY_NPCX
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help
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APB3 prescaler, allowed values: From 1 to 10.
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This sets the APB3 prescaler which changes the frequency of APB3_CLK.
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APB3_CLK frequency = OSC_CLK / APB3_PRE. The APB3 prescaler allowed
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value is from 1 to 10.
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The generated frequency of APB3_CLK should comply with the following
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requirements:
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- The frequency of APB3_CLK must be set to:
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12.5MHz <= APB3_CLK <= 50MHz.
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- The frequency of APB3_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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@ -138,6 +138,31 @@ static struct clock_control_driver_api npcx_clock_control_api = {
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.get_rate = npcx_clock_control_get_subsys_rate,
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};
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/* valid clock frequency check */
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BUILD_ASSERT(CORE_CLK <= 100000000 &&
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CORE_CLK >= 4000000 &&
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OSC_CLK % CORE_CLK == 0 &&
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OSC_CLK / CORE_CLK <= 10,
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"Invalid CORE_CLK setting");
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BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= 50000000 &&
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CORE_CLK / (FIUDIV_VAL + 1) >= 4000000,
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"Invalid FIUCLK setting");
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BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= 50000000 &&
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CORE_CLK / (AHB6DIV_VAL + 1) >= 4000000,
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"Invalid AHB6_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= 50000000 &&
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APBSRC_CLK / (APB1DIV_VAL + 1) >= 4000000 &&
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(APB1DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB1_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= 50000000 &&
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APBSRC_CLK / (APB2DIV_VAL + 1) >= 8000000 &&
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(APB2DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB2_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= 50000000 &&
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APBSRC_CLK / (APB3DIV_VAL + 1) >= 12500000 &&
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(APB3DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB3_CLK setting");
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static int npcx_clock_control_init(const struct device *dev)
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{
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struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev);
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@ -31,8 +31,8 @@ struct npcx_clk_cfg {
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* (Please refer Figure 58. for more information.)
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*
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* Suggestion:
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* - OSC_CLK >= 80MHz, XF_RANGE should be 1, else 0.
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* - CORE_CLK > 66MHz, AHB6DIV should be 1, else 0.
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* - OSC_CLK > 50MHz, XF_RANGE should be 1, else 0.
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* - CORE_CLK > 50MHz, AHB6DIV should be 1, else 0.
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* - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
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*/
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@ -46,24 +46,24 @@ struct npcx_clk_cfg {
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#define FPRED_VAL ((OSC_CLK / CORE_CLK) - 1)
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/* FMUL clock */
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#if (OSC_CLK >= 80000000)
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#define FMCLK (OSC_CLK / 2) /* FMUL clock = OSC_CLK/2 if OSC_CLK >= 80MHz */
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#if (OSC_CLK > 50000000)
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#define FMCLK (OSC_CLK / 2) /* FMUL clock = OSC_CLK/2 if OSC_CLK > 50MHz */
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#else
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#define FMCLK OSC_CLK /* FMUL clock = OSC_CLK */
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#endif
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/* APBs source clock */
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#define APBSRC_CLK OSC_CLK
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/* APB1 clock divider, default value (APB1 clock = OSC_CLK/6) */
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/* APB1 clock divider, default value (APB1 clock = OSC_CLK/4) */
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#define APB1DIV_VAL (CONFIG_CLOCK_NPCX_APB1_PRESCALER - 1)
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/* APB2 clock divider, default value (APB2 clock = OSC_CLK/6) */
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/* APB2 clock divider, default value (APB2 clock = OSC_CLK/8) */
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#define APB2DIV_VAL (CONFIG_CLOCK_NPCX_APB2_PRESCALER - 1)
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/* APB3 clock divider, default value (APB3 clock = OSC_CLK/6) */
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/* APB3 clock divider, default value (APB3 clock = OSC_CLK/2) */
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#define APB3DIV_VAL (CONFIG_CLOCK_NPCX_APB3_PRESCALER - 1)
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/* AHB6 clock */
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#if (CORE_CLK > 66000000)
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#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 66MHz */
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#if (CORE_CLK > 50000000)
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#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 50MHz */
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#else
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#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
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#endif
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@ -81,14 +81,17 @@ struct npcx_clk_cfg {
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* Frequency multiplier M/N value definitions according to the requested
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* OSC_CLK (Unit:Hz).
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*/
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#if (OSC_CLK > 80000000)
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#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
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#if (OSC_CLK > 50000000)
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#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 if OSC_CLK > 50MHz */
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#else
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#define HFCGN_VAL 0x02
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#endif
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#if (OSC_CLK == 100000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0xEC
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#elif (OSC_CLK == 96000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0x72
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#elif (OSC_CLK == 90000000)
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#define HFCGMH_VAL 0x0A
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#define HFCGML_VAL 0xBA
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@ -96,8 +99,8 @@ struct npcx_clk_cfg {
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#define HFCGMH_VAL 0x09
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#define HFCGML_VAL 0x89
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#elif (OSC_CLK == 66000000)
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#define HFCGMH_VAL 0x0F
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#define HFCGML_VAL 0xBC
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#define HFCGMH_VAL 0x07
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#define HFCGML_VAL 0xDE
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#elif (OSC_CLK == 50000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0xEC
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@ -110,12 +113,6 @@ struct npcx_clk_cfg {
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#elif (OSC_CLK == 33000000)
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#define HFCGMH_VAL 0x07
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#define HFCGML_VAL 0xDE
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#elif (OSC_CLK == 30000000)
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#define HFCGMH_VAL 0x07
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#define HFCGML_VAL 0x27
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#elif (OSC_CLK == 26000000)
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#define HFCGMH_VAL 0x06
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#define HFCGML_VAL 0x33
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#else
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#error "Unsupported OSC_CLK Frequency"
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#endif
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