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boards: shields: Support panel g1120b0mipi and rk055hdmipi4ma0 on RT700

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Add board specific overlay and configuration for display panel
g1120b0mipi and rk055hdmipi4ma0.

Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
This commit is contained in:
Kate Wang 2025-04-10 16:55:38 +08:00 • committed by Benjamin Cabé
commit 4282687d40
4 changed files with 46 additions and 0 deletions
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2
boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf Normal file
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CONFIG_REGULATOR=y
CONFIG_DCACHE=n

18
boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay Normal file
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/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
#include <zephyr/dt-bindings/display/panel.h>
&zephyr_lcdif {
status = "okay";
clock-frequency = <279000000>;
wr-period = <14>;
wr-assert = <6>;
wr-deassert = <13>;
cs-assert = <1>;
cs-deassert = <4>;
};

5
boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf Normal file
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CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM=y
CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR=0x60000000
CONFIG_MCUX_DCNANO_LCDIF_MAINTAIN_CACHE=n
CONFIG_HEAP_MEM_POOL_SIZE=40000
CONFIG_REGULATOR=y

21
boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay Normal file
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/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
&zephyr_lcdif {
compatible = "nxp,dcnano-lcdif";
version = "DC8000";
display-timings {
clock-frequency = <29333333>;
};
};
&zephyr_mipi_dsi {
/* Use lower DPHY clock since RT700 uses AUDIO pll pfd2 as source,
* and its max allowed clock frequency is
* 532.48 x 18 / 16 = 599.04MHz. In this case the 60fps cannot be used, use 30fps instead.
*/
phy-clock = <396000000>;
};